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Naji V Bekhazi

from Palo Alto, CA
Age ~59
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Also known as:
Naji Victor Bekhazi
Phone and address:
1570 University Ave, Palo Alto, CA 94301
(408) 748-0839
Related to:
Suzy BekhaziAfaf Bekhazi, 87Fuad Bekhazi
Connected to:
Mohamed E Bekheet, 63Khaled A Bekhet, 60Mohamed Bekhet, 48Maged M Bekhit, 46Mohamed I Bekhit, 75Nancy Bekhit, 38Ezra Bekhor, 74Mohammad Bekhrad, 60Nell A Bekiares, 52Chris Bekiaris, 78

Naji Bekhazi Phones & Addresses

  • 1570 University Ave, Palo Alto, CA 94301 (408) 748-0839
  • 610 Park View Dr, Santa Clara, CA 95054 (408) 748-0839
  • Bronx, NY
  • Syracuse, NY
  • 1570 University Ave, Palo Alto, CA 94301

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Resumes

Resumes

Naji Bekhazi Photo 1

Naji Bekhazi

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Location:
Palo Alto, CA
Industry:
Computer Software
Work:
Synopsys
Vice President, Engineering
Skills:
Eda
Software Engineering
Semiconductors
Tcl
Asic
Linux
Ic
Perl
Embedded Systems
Soc
Product Management
Debugging
Embedded Software
R&D
Algorithms
Fpga
Simulations
Verilog
Software Development
Application Specific Integrated Circuits
Integrated Circuits
Naji Bekhazi Photo 2

Executive Vice President Of Engineering, Products, And Operation

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Location:
Palo Alto, CA
Work:
Fanvestor
Executive Vice President of Engineering, Products, and Operation

Publications

Us Patents

Incremental Concurrent Processing For Efficient Computation Of High-Volume Layout Data

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US Patent:
8341559, Dec 25, 2012
Filed:
Nov 8, 2011
Appl. No.:
13/291856
Inventors:
Michael L. Rieger - Skamania WA, US
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tigard OR, US
Thomas Brett Hall - Portland OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 51, 716 52, 716 53, 716 55, 430 5
Abstract:
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

Incremental Concurrent Processing For Efficient Computation Of High-Volume Layout Data

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US Patent:
20100198875, Aug 5, 2010
Filed:
Jan 30, 2009
Appl. No.:
12/363674
Inventors:
Michael L. Rieger - Skamania WA, US
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tigard OR, US
Thomas Brett Hall - Portland OR, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/30
G06F 17/00
US Classification:
707793, 707E17001
Abstract:
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

Incremental Concurrent Processing For Efficient Computation Of High-Volume Layout Data

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US Patent:
20130086535, Apr 4, 2013
Filed:
Nov 26, 2012
Appl. No.:
13/685501
Inventors:
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tiard OR, US
Thomas Brett Hall - Portland OR, US
Assignee:
SYNOPSYS, INC. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 51
Abstract:
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system.

Incremental Concurrent Processing For Efficient Computation Of High-Volume Layout Data

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US Patent:
20140189616, Jul 3, 2014
Filed:
Mar 3, 2014
Appl. No.:
14/195503
Inventors:
- Mountain View CA, US
Mathias Boman - Hillsboro OR, US
Naji V. Bekhazi - Palo Alto CA, US
Daniel D. Hung - Sunnyvale CA, US
Michael G. Brashler - Tigard OR, US
Thomas Brett Hall - Portland OR, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 55
Abstract:
Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.
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Naji V Bekhazi from Palo Alto, CA, age ~59 Get Report