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Murzban D Jhabvala

from Clarksville, MD
Age ~73

Murzban Jhabvala Phones & Addresses

  • 6277 Linkythorn Ln, Clarksville, MD 21029 (410) 206-9598
  • Cincinnati, OH
  • 7142 Ashmont Cir, Fort Lauderdale, FL 33321
  • Tamarac, FL
  • Greenbelt, MD
  • Bridgeville, PA

Publications

Us Patents

Visual Aid For The Hearing Impaired

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US Patent:
50292161, Jul 2, 1991
Filed:
Jun 9, 1989
Appl. No.:
7/363807
Inventors:
Murzban D. Jhabvala - Clarksville MD
Hung C. Lin - Silver Spring MD
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics & Space Administration - Washington DC
International Classification:
H04R 2500
US Classification:
381 681
Abstract:
A multi-channel electronic visual aid device which is able to signal to the user whether sound is coming from the left or right, front or back, or both. For the plurality of channels, which may operate in pairs, the sound is picked up by a respective microphone and amplified and rectified into a DC voltage. The DC voltage is next fed to an analog to digital converter and then to a digital encoder. The binary code from the encoder is coupled into a logic circuit where the binary code is decoded to provide a plurality of output levels which are used to drive an indicator which, in turn, provides a visual indication of the sound level received. The binary codes for each pair of channels are also fed into a digital comparator. The output of the comparator is used to enable the logic circuits of the two channels such that if, for example, the signal coming from the right is louder than that coming from the left, the output of the logic unit of the right channel will be enabled and the corresponding indicator activated, indicating the sound source on the right. An indication of the loudness is also provided.

Method Of Making V-Mos Field Effect Transistors Utilizing A Two-Step Anisotropic Etching And Ion Implantation

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US Patent:
42723027, Jun 9, 1981
Filed:
Sep 5, 1979
Appl. No.:
6/072727
Inventors:
Murzban D. Jhabvala - Seabrook MD
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC
International Classification:
H01L 21265
H01L 21306
US Classification:
148 15
Abstract:
A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.

Integrated Photo-Responsive Metal Oxide Semiconductor Circuit

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US Patent:
47092521, Nov 24, 1987
Filed:
Jul 16, 1982
Appl. No.:
6/399074
Inventors:
Murzban D. Jhabvala - Seabrook MD
David R. Dargo - Arnold MD
John C. Lyons - Columbia MD
Assignee:
The United States of America as represented by the Administrator,
National Aeronautics and Space Administration - Washington DC
International Classification:
H01L 2714
H01L 29161
H01L 2978
US Classification:
357 30
Abstract:
An infrared photo-responsive element (R. sub. D) is monolithically integrated into a source follower circuit of a metal oxide semiconductor device (10) by depositing a layer of a lead chalcogenide as a photo-resistive element forming an ohmic bridge between two metallization strips (26, 28) serving as electrodes of the circuit. Voltage from the circuit varies in response to illumination of the layer by infrared radiation.

Complementary Dmos-Vmos Integrated Circuit Structure

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US Patent:
41199960, Oct 10, 1978
Filed:
Jul 20, 1977
Appl. No.:
5/817413
Inventors:
Murzban D. Jhabvala - Seabrook MD
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC
International Classification:
H01L 2978
US Classification:
357 23
Abstract:
A high speed CMOS formed on a single semiconductor substrate includes a DMOS having an asymmetric channel and a VMOS with a relatively short channel length. The short channel length of the VMOS is achieved by: (1) forming a double diffusion along one edge of a V groove, or (2) ion implanting boron into the apex of the V groove and diffusing a single layer to a relatively deep depth along both edges of the groove.

Implantable Electrical Device

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US Patent:
43088686, Jan 5, 1982
Filed:
May 27, 1980
Appl. No.:
6/153246
Inventors:
Murzban D. Jhabvala - Seabrook MD
Assignee:
The United States of America as represented by the Administrator of the
National Aeronautics and Space Administration - Washington DC
International Classification:
A61N 132
US Classification:
128421
Abstract:
A fully implantable and self-contained device is disclosed composed of a flexible electrode array 10 for surrounding damaged nerves and a signal generator 12 for driving the electrode array with periodic electrical impulses of nanoampere magnitude to induce regeneration of the damaged nerves.
Murzban D Jhabvala from Clarksville, MD, age ~73 Get Report