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Milind B Sonawane

from Santa Clara, CA
Age ~49
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Also known as:
Milind P Sonawane, Sonawane B Milind, Milind E
Connected to:
Kunal R Sonawane, 36Nilesh M Sonawane, 46Pratik S Sonawala, 46Rohit Sonawane, 42Swapnil M Sonawane, 40Nasser E Sonbaty, 60Joanne E Sonberg, 50Ayreen I Sonbol, 55Cindy G Sonboleh, 57William J Sonbuchner, 40

Milind Sonawane Phones & Addresses

  • Santa Clara, CA
  • San Jose, CA
  • Syracuse, NY
  • Milpitas, CA
  • Sunnyvale, CA

Resumes

Resumes

Milind Sonawane Photo 1

Senior Manager

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Nvidia
Senior Manager
Nvidia
Principal Engineer
Nvidia Jul 2009 - Mar 2017
Senior Dft Engineer
Lsi Corporation Nov 2003 - Jun 2009
Staff Design Engineer
Realchip Communications Inc Apr 1999 - Apr 2002
Design Engineer
Education:
National Institute of Technology Warangal 1997 - 1999
Masters, Master of Technology, Electronics Doctor Babasaheb Ambedkar Marathwada University 1993 - 1996
Bachelor of Engineering, Bachelors, Electronics Engineering Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded 1993 - 1996
Bachelor of Engineering, Bachelors, Electronics, Engineering, Communications
Skills:
Dft
Soc
Verilog
Asic
Atpg
Jtag
Bist
Vlsi
Rtl Design
Semiconductors
Dfx
Eda
Static Timing Analysis
Primetime
Physical Design
Ic
Timing Closure
Hardware Architecture
Logic Design
Lbist
Milind Sonawane Photo 2

Milind Sonawane

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Publications

Us Patents

Transition Fault Detection Register With Extended Shift Mode

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US Patent:
20060085708, Apr 20, 2006
Filed:
Oct 20, 2004
Appl. No.:
10/969086
Inventors:
Mitchael Howard - San Jose CA, US
Milind Sonawane - Sunnyvale CA, US
Jonjen Sern - Milpitas CA, US
Vicky Wu - San Jose CA, US
International Classification:
G01R 31/28
US Classification:
714726000
Abstract:
An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.

Runtime In-System Testing

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US Patent:
20220365857, Nov 17, 2022
Filed:
May 13, 2021
Appl. No.:
17/320025
Inventors:
- Santa Clara CA, US
Anitha Kalva - San Jose CA, US
Abilash Nerallapally - San Jose CA, US
Milind Sonawane - Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US
Ashok Aravamudhan - Beaverton OR, US
Sridharan Ramakrishnan - Hillsboro OR, US
Sam Edirisooriya - Milpitas CA, US
Hari Krishnan - San Carlos CA, US
International Classification:
G06F 11/263
G06F 11/27
G06F 11/273
G06F 11/14
Abstract:
During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

Performing Testing Utilizing Staggered Clocks

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US Patent:
20230089800, Mar 23, 2023
Filed:
Sep 17, 2021
Appl. No.:
17/478736
Inventors:
- Santa Clara CA, US
Venkat Abilash Reddy Nerallapally - San Jose CA, US
Jaison Daniel Kurien - Bangalore, IN
Bonita Bhaskaran - San Jose CA, US
Milind Sonawane - Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US
Purnabha Majumder - Lafayette CA, US
International Classification:
G01R 31/3177
Abstract:
During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.

Granular Dynamic Test Systems And Methods

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US Patent:
20170205465, Jul 20, 2017
Filed:
Apr 3, 2017
Appl. No.:
15/478176
Inventors:
- Santa Clara CA, US
Milind SONAWANE - San Jose CA, US
Adarsh Kalliat BALAGOPALA - Santa Clara CA, US
Amit SANGHANI - San Jose CA, US
International Classification:
G01R 31/317
G01R 31/3183
G01R 31/3185
G01R 31/3177
Abstract:
In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

Test Partition External Input/Output Interface Control

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US Patent:
20170115338, Apr 27, 2017
Filed:
Oct 27, 2016
Appl. No.:
15/336687
Inventors:
- Santa Clara CA, US
Shantanu Sarangi - Saratoga CA, US
Milind Sonawane - San Jose CA, US
Amit Sanghani - San Jose CA, US
Jonathon E. Colburn - Ben Lomond CA, US
Dan Smith - Los Gatos CA, US
Jue Wu - Los Gatos CA, US
Mahmut Yilmaz - Los Altos Hills CA, US
International Classification:
G01R 31/28
Abstract:
In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

Dynamic Independent Test Partition Clock

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US Patent:
20170115351, Apr 27, 2017
Filed:
Oct 27, 2016
Appl. No.:
15/336626
Inventors:
- Santa Clara CA, US
Anubhav Sinha - Telangana, IN
Karthikeyan Natarajan - Fremont CA, US
Shantanu Sarangi - Saratoga CA, US
Amit Sanghani - San Jose CA, US
Milind Sonawane - San Jose CA, US
Mahmut Yilmaz - Los Altos Hills CA, US
International Classification:
G01R 31/317
G01R 31/3177
Abstract:
In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

Independent Test Partition Clock Coordination Across Multiple Test Partitions

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US Patent:
20170115352, Apr 27, 2017
Filed:
Oct 27, 2016
Appl. No.:
15/336676
Inventors:
- Santa Clara CA, US
Karthikeyan Natarajan - Fremont CA, US
Shantanu Sarangi - Saratoga CA, US
Amit Sanghani - San Jose CA, US
Milind Sonawane - San Jose CA, US
Jonathon E. Colburn - Ben Lomond CA, US
Kevin Wilder - Menlo Park CA, US
Mahmut Yilmaz - Los Altos Hills CA, US
International Classification:
G01R 31/317
G01R 31/3177
Abstract:
Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

Global Low Power Capture Scheme For Cores

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US Patent:
20140189454, Jul 3, 2014
Filed:
Dec 28, 2012
Appl. No.:
13/730690
Inventors:
- Santa Clara CA, US
Milind Sonawane - San Jose CA, US
Amit D. Sanghani - San Jose CA, US
Anubhav Sinha - Hyderabad, IN
Vishal Agarwal - Sunnyvale CA, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G01R 31/3177
US Classification:
714729
Abstract:
A method for testing an integrated circuit to reduce peak power problems during scan capture mode is presented. The method comprises programming a respective duration of a first time window for each of a plurality of cores and a cache on the integrated circuit. It further comprises counting the number of pulses of a first clock signal during the first time window for each of the plurality of cores and the cache. Subsequently, the method comprises staggering capture pulses to the plurality of cores and the cache by generating pulses of a second clock signal for each of the plurality of cores and the cache during a respective second time window, wherein the number of pulses generated is based on the respective number of first clock signal pulses counted for each of the plurality of cores and the cache.
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Milind B Sonawane from Santa Clara, CA, age ~49 Get Report