US Patent:
20050209840, Sep 22, 2005
Inventors:
Mikhail Baklashov - Mountain View CA, US
International Classification:
G06F017/50
Abstract:
A method and apparatus for functional simulation of a system in a system-level simulation and verification environment using a functional language derived from a selected Scheme Language standard, and a simulator for simulating verification functions and model functions expressed in the functional language . The functional language has syntax extensions expressed as dynamic “always @” and “@” blocks, and all other event expressions which are similar to Verilog and other RTL (Register-Transfer Level) HDL (Hardware Description Language) temporal syntax constructs. A composer is further used to connect verification functions with model functions . Model functions , represented as mutable state functional objects along with selected test, monitor, checker and user-defined functions, sample reactive responses and ensure concurrent drive of abstracted signals for the simulator . The simulator can function as a formal verifier to formally verify the model functions , or a synthesizer to transform programs written in a restricted subset of the functional language into an internal control and data flow format or any synthesis-ready language. A system-level modeling and simulation environment enhanced with a graphical user interface facilitates the usage of the functional language