Search

Michael Laughery Phones & Addresses

  • 3513 Savoy Ct, Austin, TX 78738 (512) 263-1894 (512) 263-7046 (512) 363-5218
  • 11940 Battle Bridge Dr, Austin, TX 78748 (512) 233-6146
  • Slidell, LA
  • Horseshoe Bay, TX
  • 13225 Luxbury Loop, Orlando, FL 32837 (407) 888-9848
  • Nashville, TN
  • Raleigh, NC
  • Sherrills Ford, NC
  • Orange Pk, FL

Resumes

Resumes

Michael Laughery Photo 1

Sales

View page
Location:
3513 Savoy Ct, Austin, TX 78738
Industry:
Semiconductors
Work:
Ligero Technical Services Jun 2016 - Dec 11, 2016
Sales
Education:
Vanderbilt University
Languages:
English
Michael Laughery Photo 2

Michael Laughery

View page
Location:
United States

Publications

Us Patents

N-Profile Engineering At The Poly/Gate Oxide And Gate Oxide/Si Interfaces Through Nh3 Annealing Of A Layered Poly/Amorphous-Silicon Structure

View page
US Patent:
6440829, Aug 27, 2002
Filed:
Dec 30, 1998
Appl. No.:
09/223354
Inventors:
Pradip K. Roy - Orlando FL
Yi Ma - Orlando FL
Michael A. Laughery - Orlando FL
Assignee:
Agere Systems Guardian Corp. - Allentown PA
International Classification:
H01L 213205
US Classification:
438592, 438653, 438657, 438660, 438775
Abstract:
A method and structure providing N-profile engineering at the poly/gate oxide and gate oxide/Si interfaces of a layered polysilicon/amorphous silicon structure of a semiconductor device. NH annealing provides for the introduction of nitrogen to the interface, where the nitrogen suppresses Boron diffusion, improves gate oxide integrity, and reduces the sites available for trapping hot carriers which degrade device performance.

System And Method For Real-Time Library Generation Of Grating Profiles

View page
US Patent:
6768983, Jul 27, 2004
Filed:
Nov 28, 2000
Appl. No.:
09/727530
Inventors:
Nickhil Jakatdar - Los Altos CA
Michael Laughery - Austin TX
Assignee:
Timbre Technologies, Inc. - Santa Clara CA
International Classification:
G06N 502
US Classification:
706 46, 706 20
Abstract:
The present invention provides a method and a system for a real-time configurable definition and generation of grating profile libraries. A parameter set is used to specify the ranges of grating dimensions and resolutions of the profile library to be generated. In one embodiment, a compiler creates subsets of a large profile library, the subset designed to enable rapid search and validation of real-time data. In another embodiment, an automatic process generates a new parameter set and a new subset of the library when trigger conditions are met. Subsets of the profile library may be used to check if grating spectrum data are within the ranges established for an application and if the dimensions are within the process averages established for a manufacturing run. The system for generation of grating profile libraries is scalable, operable in a distributed environment, and includes application specific items that can be selected or determined by the client.

Metrology Diffraction Signal Adaptation For Tool-To-Tool Matching

View page
US Patent:
6792328, Sep 14, 2004
Filed:
Mar 29, 2002
Appl. No.:
10/109955
Inventors:
Michael Laughery - Austin TX
David Wasinger - Scottsdale AZ
Nickhil Jakatdar - Los Altos CA
Assignee:
Timbre Technologies, Inc. - Santa Clara CA
International Classification:
G06F 1900
US Classification:
700121, 348 14
Abstract:
A method and system in integrated circuit metrology for adapting a metrology system to work with diverse metrology devices. One embodiment is a method and system for generating signal adjustment data to adapt measured diffraction signals to enable use of a library of diffraction signals and structure profiles created for a different metrology device. Another embodiment is the creation and use of a data store of diffraction adjustment vectors and metrology device specifications relative to a reference device specification.

Selection Of Wavelengths For Integrated Circuit Optical Metrology

View page
US Patent:
7474993, Jan 6, 2009
Filed:
Apr 20, 2007
Appl. No.:
11/788735
Inventors:
Srinivas Doddi - Fremont CA, US
Lawrence Lane - San Jose CA, US
Vi Vuong - Fremont CA, US
Michael Laughery - Austin TX, US
Junwei Bao - Palo Alto CA, US
Kelly Barry - Saratoga CA, US
Nickhil Jakatdar - Los Altos CA, US
Emmanuel Drege - San Jose CA, US
Assignee:
Timbre Technologies, Inc. - Santa Clara CA
International Classification:
G01R 13/00
G01R 31/26
US Classification:
702196, 702 66, 702159, 702172, 438 16
Abstract:
Specific wavelengths to use in optical metrology of an integrated circuit can be selected using one or more selection criteria and termination criteria. Wavelengths are selected using the selection criteria, and the selection of wavelengths is iterated until the termination criteria are met.

In-Situ Boron Doped Polysilicon With Dual Layer And Dual Grain Structure For Use In Integrated Circuits Manufacturing

View page
US Patent:
61627119, Dec 19, 2000
Filed:
Jan 15, 1999
Appl. No.:
9/232114
Inventors:
Yi Ma - Orlando FL
Stefanie Chaplin - Tempe AZ
Stephen Carl Kuehne - Orlando FL
Brittin Charles Kane - Clermont FL
Michael A. Laughery - Orlando FL
Assignee:
Lucent Technologies, Inc. - Murray Hill NJ
International Classification:
H01L 2120
US Classification:
438558
Abstract:
A method and structure providing a dual layer silicon gate film having a uniform boron distribution therein and an ordered, uniform grain structure. Rapid thermal annealing is used to cause the diffusion of boron from an originally doped film to an originally undoped film, resulting in a uniform boron distribution within the structure, thereby rendering the structure resistant to vertical and lateral diffusion of the boron during subsequent processing at elevated temperatures.

Method For Forming A Nitride Layer Suitable For Use In Advanced Gate Dielectric Materials

View page
US Patent:
61773638, Jan 23, 2001
Filed:
Sep 29, 1998
Appl. No.:
9/162542
Inventors:
Pradip K. Roy - Orlando FL
Yi Ma - Orlando FL
Michael A. Laughery - Orlando FL
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H01L 21336
H01L 2131
US Classification:
438791
Abstract:
A method for forming a gate dielectric for use in ultra-thin integrated circuit environments includes forming a nitride layer under conditions effective to introduce defects in the nitride layer. The nitride layer is formed so as to have a defect density which is sufficiently large to provide a low interfacial trap density, particularly after annealing, and thus eliminate the charge trap problems associated with traditional nitride layers. This nitride layer can be used in, for example, ON or ONO structures, which can themselves be employed as a gate dielectric. The ON and ONO structures are preferably formed under low temperature and low pressure conditions to more effectively control oxide and nitride formation. This allows for the formation of gate dielectrics that are less than 10 nm in thickness. Moreover, these ultra-thin dielectrics can be formed in a single furnace cluster.
Michael A Laughery from Austin, TX, age ~52 Get Report