Inventors:
Matthew E. Aubertine - Austin TX
Kianoush Beyzavi - Cary NC
Harold J. Broker - Ulster Park NY
Ronald P. Checca - LaGrangeville NY
Michael A. Granato - Poughkeepsie NY
David A. Haeussler - Cary NC
Michael Herasimtschuk - Poughkeepsie NY
Michael J. Jurkovic - Lagrange NY
Gerard M. Salem - Highland NY
Craig R. Selinger - Spring Valley NY
Paul R. Zehr - Claverack NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1517
G06F 1126
Abstract:
A method is provided to assign component I/O (input/output, the interface area between levels of physical packaging) pins for all components at each level of the computer system. In a hierarchical, top-down design methodology, the I/O pins for each computer system component are assigned to nets (a net is an interconnection of pins on a level of packaging, or between levels of packaging) based on wire length, electrical limits and timing. Parameters that are considered are net priority (the importance of this net to the system, relative to other nets in the system), location of physical components, location of physical component I/Os at all computer system levels of physical packaging hierarchy, and I/O pin characteristics. An iterative method is used to assign and reassign I/O pins at each level based on timing. As I/Os are reassigned at each lower component level, new assignments are made at all higher levels of the system packaging hierarchy based on the changed parameters at the lower level.