Michael Patrick Chudzik

6361598, Mar 26, 2002

Jul 20, 2000

09/621272

Uthamalingam Balachandran - Hinsdale IL
Michael P. Chudzik - Beacon NY

The University of Chicago - Chicago IL

C30B 2502

117 86, 117 84, 117947, 4272481

A method of depositing a biaxially textured metal oxide on a substrate defining a plane in which metal oxide atoms are vaporized from a source to form a plume of metal oxide atoms. Atoms in the plume disposed at a selected angle in a predetermined range of angles to the plane of the substrate are allowed to contact the substrate while preventing atoms outside a selected angle from reaching the substrate. The preferred range of angles is 40Â-70Â and the preferred angle is 60ÂÂ5Â. A moving substrate is disclosed.

6451662, Sep 17, 2002

Oct 4, 2001

09/970635

Michael Chudzik - Beacon NY
Oleg Gluschenkov - Wappingers Falls NY
Raj Jammy - Wappinger Falls NY
Uwe Schroeder - Dresden, GB
Helmut Tews - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

H01L 2120

438386, 438240, 438393, 438775

An improved capacitor is formed by a process where an improved node dielectric layer is formed with an improved dielectric constant by performing an Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step during formation of the node dielectric layer. Use of an FRE RTO step instead of the conventional furnace oxidation step produces a cleaner oxide with a higher dielectric constant and higher capacitance. Other specific embodiments of the invention include improved node dielectric layer by one or more additional nitridation steps, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; use of a metal layer rather than a SiN layer as the dielectric base; and selective oxidation of the metal layer.

6541331, Apr 1, 2003

Aug 9, 2001

09/924548

Michael P. Chudzik - Beacon NY
Lawrence Clevenger - LaGrangeville NY
Louis L. Hsu - Fishkill NY
Deborah A. Neumayer - Danbury CT

International Business Machines Corporation - Armonk NY

H01L 218242

438240, 438396, 438608, 257410, 257411

A process of forming a high-k dielectric in an integrated circuit structure is disclosed. The process cleans a substrate to remove residual organic materials and strip native oxide from the surface of the substrate. Next, the process introduces precursors on the substrate in molar ratios consistent with formation of dielectric glass films. Following that, the process oxidizes the precursors, heats the precursors, and cools the precursors at a rate that avoids crystallization of the precursors.

6555430, Apr 29, 2003

Nov 28, 2000

09/723420

Michael P. Chudzik - Beacon NY
Johnathan Faltermeier - Lagrange NY
Rajarao Jammy - Wappingers Falls NY
Stephan Kudelka - Fishkill NY
Irene McStay - Hopewell Junction NY
Helmut Horst Tews - Poughkeepsie NY

International Business Machines Corporation - Armonk NY

H01L 218242

438243, 438212, 438245, 438386, 438589, 438665, 438964

Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

6579759, Jun 17, 2003

Aug 23, 2002

10/227396

Michael Patrick Chudzik - Beacon NY
Jochen Beintner - Wappingers Falls NY
Ramachandra Divakaruni - Ossining NY
Rajarao Jammy - Wappingers Falls NY

International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich

H01L 218242

438249, 438270, 438589

In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

6653246, Nov 25, 2003

Jan 8, 2003

10/338481

Michael P. Chudzik - Beacon NY
Lawrence Clevenger - LaGrangeville NY
Louis L. Hsu - Fishkill NY
Deborah A. Neumayer - Danbury CT

International Business Machines Corporation - Armonk NY

H01L 2131

438785, 257303, 257310, 257410, 257411

A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate. The introducing of precursors is performed in molar ratios consistent with formation of glass films and may comprise an atomic level chemical vapor deposition of La O and Al O using ratios between 20%-50% La O and 50%-80%.

6664161, Dec 16, 2003

May 1, 2002

10/137268

Michael Patrick Chudzik - Beacon NY
Jack Allan Mandelman - Stormville NY
Carl John Radens - LaGrangeville NY
Rajarao Jammy - Wappingers Falls NY
Padraic C. Shafer - Beacon NY

International Business Machines Corporation - Armonk NY

H01L 218242

438243, 438244, 438386

The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.

6759292, Jul 6, 2004

Oct 30, 2002

10/283483

Mihel Seitz - Dresden, DE
Michael P. Chudzik - Beacon NY
Jack A. Mandelman - Flat Rock NC

Infineon Technologies AG
International Business Machines Corporation - Armonk NY

H01L 218242

438243, 438386

A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.