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Mehrdad X Heshami

from Sunnyvale, CA
Age ~61
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Also known as:
Mehrdad Hesami
Phone and address:
1112 Polk Ave, Sunnyvale, CA 94086
(925) 519-0171
Connected to:
Kourosh Heshmati, 65Parissa Heshmati, 58Shohreh Heshmati, 63Deneen K Hesia, 40Patrick D Hesidence, 59Monica A Hesik, 59Amanda L Hesington, 35Paige M Heskamp, 34Christopher R Heske, 34Suzanne B Heske, 54

Mehrdad Heshami Phones & Addresses

  • 1112 Polk Ave, Sunnyvale, CA 94086 (925) 519-0171
  • Santa Clara, CA
  • San Jose, CA
  • Stanford, CA
  • Warrenton, VA
  • Mountain View, CA
  • 1112 Polk Ave, Sunnyvale, CA 94086

Publications

Us Patents

Cmos Controlled-Impedance Transmission Line Driver

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US Patent:
6909310, Jun 21, 2005
Filed:
Jan 30, 2003
Appl. No.:
10/354281
Inventors:
Kenneth D. Poulton - Palo Alto CA, US
Robert M. R. Neff - Palo Alto CA, US
Jorge A. Pernillo - Daly City CA, US
Mehrdad Heshami - Palo Alto CA, US
Assignee:
Agilent Technologies, Inc. - Palo Alto CA
International Classification:
H03B001/00
US Classification:
327108, 327563, 327 65
Abstract:
A line driver fabricated from CMOS devices that provides a substantially constant output impedance over a significant range of a time-varying input voltage includes a time-varying current source, a pair of CMOS output loads, and a pair of biasing circuits. Each CMOS output load includes a NMOS transistor and a PMOS transistor connected in parallel and each biased into a linear range of operation. In response to a time-varying input voltage, the time-varying current source draws current from the pair of CMOS output loads in a manner that operates each CMOS output load to collectively establish a time-varying output voltage component at an associated output terminal.

Variable Frequency Clock Generator For Synchronizing Data Rates Between Clock Domains In Radio Frequency Wireless Communication Systems

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US Patent:
7389095, Jun 17, 2008
Filed:
May 18, 2005
Appl. No.:
11/132978
Inventors:
Tao Liu - Sunnyvale CA, US
Mansour Keramat - San Jose CA, US
Edward Wai Yeung Liu - Milpitas CA, US
Mehrdad Heshami - Palo Alto CA, US
Timothy C. Kuo - Cupertino CA, US
Assignee:
Nvidia Corporation - Santa Clara CA
International Classification:
H04B 1/06
US Classification:
455260, 455323, 455333, 375346, 331 16
Abstract:
A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Analog-To-Digital Converter Architecture Using A Capacitor Array Structure

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US Patent:
7403150, Jul 22, 2008
Filed:
Sep 20, 2006
Appl. No.:
11/524989
Inventors:
Mehrdad Heshami - Palo Alto CA, US
Mansour Keramat - San Jose CA, US
Assignee:
Alvand Technologies, Inc. - Santa Clara CA
International Classification:
H03M 1/36
US Classification:
341159, 341155, 341158, 341172
Abstract:
An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure. The comparator device array further includes multiple comparator devices coupled in parallel, each comparator device having a pair of inputs coupled to the switched capacitor circuit structure to receive a voltage output signal from the switched capacitor circuit, a voltage value of the voltage output signal being calculated as a difference between an input voltage value of the input voltage signal and a predetermined value of the reference voltage signal, which is dependent on the position of the respective comparator device within the comparator device array, each comparator device experiencing an identical common mode voltage input within the analog-to-digital converter circuit.

Fabricated Layered Capacitor For A Digital-To-Analog Converter

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US Patent:
7446365, Nov 4, 2008
Filed:
Mar 7, 2006
Appl. No.:
11/371257
Inventors:
Mehrdad Heshami - Palo Alto CA, US
Mansour Keramat - San Jose CA, US
Assignee:
Alvand Technologies, Inc. - Santa Clara CA
International Classification:
H01L 27/108
US Classification:
257303, 257296, 257298, 257306, 257307, 257308, 341150
Abstract:
A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e. g. , five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Fabricated U-Shaped Capacitor For A Digital-To-Analog Converter

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US Patent:
7456462, Nov 25, 2008
Filed:
Mar 7, 2006
Appl. No.:
11/371145
Inventors:
Mehrdad Heshami - Palo Alto CA, US
Mansour Keramat - San Jose CA, US
Assignee:
Alvand Technologies, Inc. - Santa Clara CA
International Classification:
H01L 29/94
US Classification:
257307, 257296, 257298, 257306, 257308, 257E21648, 341150
Abstract:
A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.

Fabricated Cylinder Capacitor For A Digital-To-Analog Converter

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US Patent:
7473955, Jan 6, 2009
Filed:
Mar 7, 2006
Appl. No.:
11/371148
Inventors:
Mehrdad Heshami - Palo Alto CA, US
Mansour Keramat - San Jose CA, US
Assignee:
Alvand Technologies, Inc. - Santa Clara CA
International Classification:
H01L 29/94
US Classification:
257307, 257296, 257298, 257306, 257308, 341150
Abstract:
A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.

Variable Frequency Clock Generator For Synchronizing Data Rates Between Clock Domains In Radio Frequency Wireless Communication Systems

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US Patent:
7499690, Mar 3, 2009
Filed:
Dec 12, 2007
Appl. No.:
11/954857
Inventors:
Tao Liu - Sunnyvale CA, US
Mansour Keramat - San Jose CA, US
Edward Wai Yeung Liu - Milpitas CA, US
Mehrdad Heshami - Palo Alto CA, US
Timothy C. Kuo - Cupertino CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04B 1/06
US Classification:
455260, 455324, 375327, 331 19
Abstract:
A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Variable Frequency Clock Generator For Synchronizing Data Rates Between Clock Domains In Radio Frequency Wireless Communication Systems

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US Patent:
7542749, Jun 2, 2009
Filed:
Dec 12, 2007
Appl. No.:
11/955101
Inventors:
Tao Liu - Sunnyvale CA, US
Mansour Keramat - San Jose CA, US
Edward Wai Yeung Liu - Milpitas CA, US
Mehrdad Heshami - Palo Alto CA, US
Timothy C. Kuo - Cupertino CA, US
Assignee:
NVIDIA Corporation - Santa Clara CA
International Classification:
H04B 1/06
US Classification:
455260, 375327, 331 19
Abstract:
A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.
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Mehrdad X Heshami from Sunnyvale, CA, age ~61 Get Report