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Meeling R Roberts

from San Mateo, CA
Age ~66
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Also known as:
Meeling Ro Erts, Meeling R Fung, Meeling K Fung, Mary Roberts
Related to:
Robert P Fung, 64Honming Ming Fung, 95Kit Fung, 87Vincent Fung, 51Wingcho Fung Cho, 67Chongkit An FungKwaifun Tsun Fung, 92Garret Y Fung, 82
Connected to:
Abbie I Roberts, 60Adam C Roberts, 44Adam Roberts, 62Addam K Roberts, 35Adonnica L Roberts, 61Adrian Robertson, 53Adrianne C Robertson, 35Adrianne L Roberts, 44Agnes R Roberts, 70Ahna N Roberts, 44

Meeling Roberts Phones & Addresses

  • San Mateo, CA
  • Fremont, CA
  • San Francisco, CA
  • San Jose, CA
  • Alameda, CA
  • 44058 Owl Dr, Fremont, CA 94539

Work

Position: Technicians and Related Support Occupations

Education

Degree: Associate degree or higher

Publications

Us Patents

Slow Memory Refresh In A Computer With A Limited Supply Of Power

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US Patent:
54653673, Nov 7, 1995
Filed:
Jul 19, 1994
Appl. No.:
8/277771
Inventors:
Chandrashekar M. Reddy - Santa Clara CA
Scott D. Hirose - San Jose CA
Sung-Soo Cho - Sunnyvale CA
James P. Kardach - San Jose CA
Steven M. Farrer - Santa Clara CA
Meeling Roberts - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 132
US Classification:
395750
Abstract:
A power suspend mode activates a slow DRAM refresh in a computer system with a limited source of power. The power suspend mode reduces the power consumed by the computer system while preserving the contents of memory. The cyclic refresh of DRAM using a slow refresh clock substantially reduces the power consumed while the computer is suspended. This technique is particularly useful for battery powered portable computer systems. When an external or internal condition causes the computer system to transition to a power down mode, an IO subsystem notifies the CPU which sets control bits in the IO subsystem and a video subsystem. The IO subsystem then begins to generate a slow DRAM refresh pulse. Once the CPU and video subsystem sense the power suspend mode activation, the system memory and video memory are refreshed using the slow refresh clock. The power consumed during the refresh process is thereby greatly reduced.

Apparatus For Translating Logic Signal Levels From 3.3 Volts To 5 Volts

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US Patent:
54225230, Jun 6, 1995
Filed:
Sep 22, 1993
Appl. No.:
8/125542
Inventors:
Meeling Roberts - Fremont CA
Ronald J. Mayer - Folsom CA
Waleed S. Almulla - Folsom CA
Bradley G. Heaney - Mountain View CA
Gloria Leong - San Mateo CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 5003
US Classification:
326 68
Abstract:
An apparatus having a 3. 3 volt power supply and a 5 volt power supply, wherein digital signals are processed on a 3. 3 volt basis which are translated to a 5 volt basis by a voltage translation circuit before being output. The voltage translator is comprised of an inverter for inverting an input signal. The inverter is powered by the 3. 3 volt power supply. A p-channel transistor having its source coupled to the 5 volt power supply and its gate driven by the output of the inverter is implemented. When the inverter generates a low logic, the p-channel transistor is turned on and outputs 5 volts. An n-channel transistor having its source coupled to ground and its gate driven by the output of the inverter is also implemented. When the output of the inverter is 3. 3 volts, the n-channel transistor is turned on, which pulls the output to ground.
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Meeling R Roberts from San Mateo, CA, age ~66 Get Report