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Maxim Klebanov Phones & Addresses

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  • 52 Burning Bush Dr, Palm Coast, FL 32137
  • 112 Arlington St #1, Manchester, NH 03104
  • Waltham, MA
  • 33 Wesley St, Newton, MA 02458 (617) 965-1408
  • Worcester, MA
  • Shrewsbury, MA
  • 33 Wesley St, Newton, MA 02458

Publications

Us Patents

Method And Apparatus To Improve Esd Robustness Of Power Clamps

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US Patent:
20130335868, Dec 19, 2013
Filed:
Jun 15, 2012
Appl. No.:
13/524027
Inventors:
Washington Lamar - Mont Vernon NH, US
Maxim Klebanov - Newton MA, US
Assignee:
Allegro Microsystems, Inc. - Worcester MA
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
A power clamp circuit having improved robustness to electrostatic discharge (ESD) events includes a voltage regulation circuit and a current controlled switch. The voltage regulation circuit and the current controlled switch may be used to modify a snapback voltage of the power clamp in a manner that enhances the power clamp's ability to handle ESD events.

Dual Circuit Digital Isolator

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US Patent:
20230084169, Mar 16, 2023
Filed:
Oct 31, 2022
Appl. No.:
18/051151
Inventors:
- Manchester NH, US
Maxim Klebanov - Palm Coast FL, US
Cory Voisine - Manchester NH, US
Kenneth Snowdon - Stratham NH, US
Hsuan-Jung Wu - Taoyuan City, TW
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
H01L 23/522
H01L 21/8234
Abstract:
An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

Electronic Circuit Structure And Method Of Fabricating Electronic Circuit Structure Having Magnetoresistance Element With Improved Electrical Contacts

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US Patent:
20210057642, Feb 25, 2021
Filed:
Nov 5, 2020
Appl. No.:
17/089798
Inventors:
- Manchester NH, US
Maxim Klebanov - Manchester NH, US
Bryan Cadugan - Bedford NH, US
Sundar Chetlur - Bedford NH, US
Harianto Wong - Southborough MA, US
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
H01L 43/12
Abstract:
An apparatus including a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.

Electronic Circuit Structure And Method Of Fabricating Electronic Circuit Structure Having Magnetoresistance Element With Improved Electrical Contacts

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US Patent:
20200266337, Aug 20, 2020
Filed:
Feb 20, 2019
Appl. No.:
16/280199
Inventors:
- Manchester NH, US
Maxim Klebanov - Waltham MA, US
Bryan Cadugan - Bedford NH, US
Sundar Chetlur - Bedford NH, US
Harianto Wong - Southborough MA, US
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
H01L 43/12
Abstract:
A manufacturing method results in a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.

Patterning Of A Magnetoresistance Structure Including Two Hard Masks

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US Patent:
20200075846, Mar 5, 2020
Filed:
Sep 5, 2018
Appl. No.:
16/122019
Inventors:
- Manchester NH, US
Maxim Klebanov - Manchester NH, US
Paolo Campiglio - Arcueil, FR
Sundar Chetlur - Bedford NH, US
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
H01L 43/12
H01L 43/08
H01L 43/10
Abstract:
A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask. The method further includes patterning the second photoresist to expose portions of the second hard mask, etching the exposed portions of the second hard mask, stripping the second photoresist, etching a portion of the second hard mask, a portion of the etch barrier and the base to form a second intermediate structure, and depositing a capping barrier on the second intermediate structure.

Methods And Apparatus For Electrical Overstress Protection

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US Patent:
20200076189, Mar 5, 2020
Filed:
Aug 29, 2018
Appl. No.:
16/115901
Inventors:
- Manchester NH, US
Maxim Klebanov - Waltham MA, US
Sundar Chetlur - Bedford NH, US
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
H02H 9/04
H02H 1/00
Abstract:
An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

Metal-Oxide Semiconductor (Mos) Device Structure Based On A Poly-Filled Trench Isolation Region

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US Patent:
20190363162, Nov 28, 2019
Filed:
Aug 12, 2019
Appl. No.:
16/537725
Inventors:
- Manchester NH, US
Maxim Klebanov - Manchester NH, US
Washington Lamar - Mont Vernon NH, US
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
H01L 29/08
H01L 29/06
H01L 29/51
H01L 29/78
H01L 27/088
H01L 29/423
Abstract:
A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

Angle Sensor Using Eddy Currents

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US Patent:
20190265018, Aug 29, 2019
Filed:
Feb 22, 2019
Appl. No.:
16/282539
Inventors:
- Manchester NH, US
Maxim Klebanov - Manchester NH, US
Assignee:
Allegro MicroSystems, LLC - Manchester NH
International Classification:
G01B 7/30
G01R 33/00
G01R 33/028
G01R 33/06
Abstract:
Methods and apparatus for a sensor with a main coil to direct a magnetic field at a rotating target for inducing eddy currents in an end of the target and a sensing element to detect a magnetic field reflected from the target, wherein the target end comprises a conductive surface. The reflected magnetic field can be processed to determine an angular position of the target.
Maxim P Klebanov from Palm Coast, FL, age ~53 Get Report