Matthias Larry Tam

43474764, Aug 31, 1982

Dec 4, 1980

6/212783

Matthias L. Tam - Monterey Park CA

Rockwell International Corporation - El Segundo CA

G05F 320

323313

A voltage and temperature insensitive reference circuit voltage source for predetermining the proportion of supply voltage to constitute the output voltage including a pull-up device and a pull-down device connected between a source of supply voltage and a reference point. A two element biasing circuit is connected between the source and the pull-down device which is connected to the reference point with the pull-up device comprising a FET having a gate. A connection extends from the biasing circuit at a point between its elements to the gate. An output connection extends from the junction of the pull-up and pull-down device. One of the elements which is connected between the source and the other of the elements is characterized by high resistance relative to the other of the elements whereby the proportion of voltage available at the output connection remains substantially constant regardless of source voltage variation and ambient temperature.

44198086, Dec 13, 1983

Sep 23, 1982

6/421757

Matthias L. Tam - Monterey Park CA
Frank Z. Custode - Norco CA

Rockwell International Corporation - El Segundo CA

H01L 21225
H01L 21265

29571

The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

44045816, Sep 13, 1983

Dec 15, 1980

6/216578

Matthias L. Tam - Monterey Park CA
Frank Z. Custode - Norco CA

Rockwell International Corporation - El Segundo CA

H01L 2904
H01L 2912
H01L 2978
H01L 2702

357 59

The present invention comprises a unique FET with resistor in its drain lead of undoped polysilicon which may be characterized by high resistance in the absence of the application of a biasing voltage across the FET and the resistor when the FET is conducting, which biasing voltage irreversibly changes the resistor to a high state of conductivity thereby selectively providing the two logic states. This device may comprise a redundant cell for a ROM memory and may be uniquely fabricated utilizing VLSI MOS processing steps to provide a new manufacturing process.

45934533, Jun 10, 1986

Jun 18, 1984

6/621773

Matthias L. Tam - Monterey Park CA
Frank Z. Custode - Norco CA

Rockwell International Corporation - El Segundo CA

H01L 2978
H01L 21425

29571

The invention relates to the process for manufacturing and the structure of stacked transistors on a silicon substrate wherein a polysilicon layer is employed which is recrystallized and delineated to form the gate for one transistor and the source, channel and drain for the complementary transistor which is totally formed using isolating field oxide as its substrate.

42310512, Oct 28, 1980

Jun 6, 1978

5/913258

Frank Z. Custode - Norco CA
Matthias L. Tam - Monterey Park CA

Rockwell International Corporation - El Segundo CA

H01L 2978

357 23

A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for diffused conducting lines in the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having oxidation and etch characteristics permits selective oxidation of desired portions only of the structure without need for masking, and removal of selected material from desired locations by batch removal processes again without use of masking. There results semiconductor devices of minimum geometry with selective interconnection capabilities, affording VLSI circuits having increased density with improved yield and reliability.

44060491, Sep 27, 1983

Jul 12, 1982

6/397647

Matthias L. Tam - Monterey Park CA
Frank Z. Custode - Norco CA

Rockwell International Corporation - Anaheim CA

H01L 2122
H01L 21265

29571

The subject invention conserves memory real estate by employing ROM cells which are FETs or non-FETs depending upon the programming. Each cell comprises a gate, a source and drain region and provision for connections to bit and word lines. Programming is achieved by a mask which permits doping of the source and drain regions to comprise FETs for the cells indicative of one state of logic while precluding doping of the source and drain regions to complete the channel in the cells comprising the other state of logic. Also, the FETs are fabricated, their contacts extending linearly between bit lines which are preferably diffused lines, and the word line making direct contact with gates of the linear cells. The process simplifies the number of steps required to manufacture the FETs and non-FETs by simply providing the programming after the basic cells are formed. Such unprogrammed structures may be inventoried and simply programmed i. e.