Matthias D Heizmann

20170168825, Jun 15, 2017

Aug 24, 2016

15/245280

- Armonk NY, US
Matthias D. Heizmann - Poughkeepsie NY, US
Brian R. Prasky - Campbell Hall NY, US

G06F 9/30
G06F 9/38

According to an aspect, management of auxiliary branch prediction in a processing system including a primary branch predictor and an auxiliary branch predictor is provided. A congruence class of the auxiliary branch predictor is located based on receiving a primary branch predictor misprediction indicator corresponding to a mispredicted target address of the primary branch predictor. An entry is identified in the congruence class having an auxiliary usefulness level set to a least useful level with respect to one or more other entries of the congruence class. Auxiliary data corresponding to the mispredicted target address is installed into the entry. The auxiliary usefulness level of the entry is reset to an initial value based on installing the auxiliary data.

20170168828, Jun 15, 2017

Jun 28, 2016

15/194898

- Armonk NY, US
Adam B. Collura - Hopewell Junction NY, US
Matthias D. Heizmann - Poughkeepsie NY, US
Daniel Lipetz - Flushing NY, US
Brian R. Prasky - Campbell Hall NY, US

G06F 9/38
G06F 9/30

According to an aspect, virtualized weight perceptron branch prediction is provided in a processing system. A selection is performed between two or more history values at different positions of a history vector based on a virtualization map value that maps a first selected history value to a first weight of a plurality of weights, where a number of history values in the history vector is greater than a number of the weights. The first selected history value is applied to the first weight in a perceptron branch predictor to determine a first modified virtualized weight. The first modified virtualized weight is summed with a plurality of modified virtualized weights to produce a prediction direction. The prediction direction is output as a branch predictor result to control instruction fetching in a processor of the processing system.

20170083342, Mar 23, 2017

Dec 9, 2016

15/373510

- Armonk NY, US
Jatin Bhartia - Uttar Pradesh, IN
Akash V. Giri - Austin TX, US
Matthias Heizmann - Poughkeepsie NY, US

G06F 9/38

A method comprises identifying a number of branches (N) and a number of iterations (N) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals N, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than N−1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than N, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

20170003968, Jan 5, 2017

Mar 30, 2016

15/084884

- Armonk NY, US
Jatin Bhartia - Uttar Pradesh, IN
Akash V. Giri - Austin TX, US
Matthias Heizmann - Poughkeepsie NY, US

G06F 9/38
G06F 9/30

A method comprises identifying a number of branches (N) and a number of iterations (N) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals N, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than N−1, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than N, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

20170003970, Jan 5, 2017

Jul 1, 2015

14/789065

- Armonk NY, US
Jatin Bhartia - Uttar Pradesh, IN
Akash V. Giri - Austin TX, US
Matthias Heizmann - Poughkeepsie NY, US

G06F 9/38

A method comprises identifying a number of branches (N) and a number of iterations (N) in a loop in an instruction stream, generating a number of forward branches until the number of forward branches equals N, generating a non-branch instruction in between the forward branch instruction, recording in a memory, instruction stream generated and a history of each branch, an associated target address of each branch, and whether the branch is a taken branch or a not taken branch, determining whether a loop iterator number (i) is less than N, generating a backward branch with a target address which is greater than or equal to the start address and is lesser than the current address responsive to determining that (i) is less than N, and recording in the memory, a branch instruction of the generated backward branch and the associated target address of the backward branch.

20170004023, Jan 5, 2017

Jul 1, 2015

14/789402

- Armonk NY, US
Matthias D. Heizmann - Poughkeepsie NY, US
Parminder Singh - Bangalore, IN

G06F 9/54
G06F 11/30
G06F 11/34

Embodiments include a method, system, and computer program product for verifying a counter design. A method includes receiving a plurality of events within the counter design. The plurality of events can include a context event and a design event. The method also includes determining a tolerance window in response to the receiving of the context. The tolerance window is defined around the context event and includes a first portion before an occurrence of the context event and a second portion after the context event. The method further includes performing a verification algorithm to identify whether the design event is within the tolerance window and should be accounted for by a design model counter of the counter design.

20170004024, Jan 5, 2017

Mar 17, 2016

15/073173

- Armonk NY, US
Matthias D. Heizmann - Poughkeepsie NY, US
Ajit S. Honnungar - Poughkeepsie NY, US
Parminder Singh - Bangalore, IN

G06F 9/54
G06F 11/34

Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.

20170004061, Jan 5, 2017

Sep 8, 2016

15/259757

- Armonk NY, US
Matthias D. Heizmann - Poughkeepsie NY, US
Ajit S. Honnungar - Poughkeepsie NY, US
Parminder Singh - Bangalore, IN

G06F 11/22
G06F 11/273

Embodiments include a method for verifying a counter design within a tolerance window within which a race condition occurs between a context event and a design event. The method includes receiving a plurality of events within the counter design, the plurality of events including the context event and the design event. The method also includes dynamically determining the tolerance window around the context event by setting a first portion of the tolerance window to precede an occurrence of the context event and by setting a second portion of the tolerance window to follow the context event. Additionally, the method includes performing a verification of whether the design event is within the first portion of the tolerance window or the second portion of the tolerance window.