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Matthew Baecher Phones & Addresses

  • 10 Oak Hill Dr, Rock Tavern, NY 12575
  • 165 Isis Dr, Newburgh, NY 12550 (845) 566-3328
  • Monroe, NY
  • Rochester, NY
  • Bradley Beach, NJ

Publications

Us Patents

System And Method Of Digitally Testing An Analog Driver Circuit

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US Patent:
7659740, Feb 9, 2010
Filed:
Aug 11, 2008
Appl. No.:
12/189226
Inventors:
Joseph O. Marsh - Poughkeepsie NY, US
Jeremy Stephens - Seattle WA, US
Charlie C. Hwang - Wappingers Falls NY, US
James S. Mason - Eastleigh, GB
Huihao Xu - Brooklyn NY, US
Matthew B. Baecher - Newburgh NY, US
Thomas J. Bardsley - Poughkeepsie NY, US
Mark R. Taylor - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/02
G01R 31/26
US Classification:
324763, 324765
Abstract:
Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.

Low Power Digital Adaptive Termination Network

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US Patent:
20050083079, Apr 21, 2005
Filed:
Oct 7, 2004
Appl. No.:
10/960142
Inventors:
Matthew Baecher - Newburgh NY, US
James Mason - Eastleigh, GB
International Classification:
H03K019/003
US Classification:
326030000
Abstract:
An apparatus, method, microprocessor device and computer program for configuring a termination network of a communication device includes a voltage comparator for comparing a voltage across the termination network with a reference voltage; a logic arrangement for setting a digital control vector in response to a state returned by said voltage comparator; and a first switching apparatus for activating a first weighted-value resistor in response to the setting of the digital control vector. At least a second switching apparatus for activating a second weighted-value resistor, and wherein each of the first and the second weighted-value resistors is represented by a value in the digital control vector may be provided, the first and second resistors are connected in series or in parallel. The digital control vector may be stored in a logic register and distributed to a plurality of termination networks. The logic arrangement may include a finite state machine.

System And Method Of Digitally Testing An Analog Driver Circuit

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US Patent:
20050246125, Nov 3, 2005
Filed:
Mar 25, 2004
Appl. No.:
10/708788
Inventors:
Joseph Marsh - Poughkeepsie NY, US
Jeremy Stephens - Seattle WA, US
Charlie Hwang - Wappingers Falls NY, US
James Mason - Eastleigh, Hampshire, GB
Huihao Xu - Brooklyn NY, US
Matthew Baecher - Newburgh NY, US
Thomas Bardsley - Poughkeepsie NY, US
Mark Taylor - Essex Junction VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
G06F019/00
US Classification:
702117000
Abstract:
A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal. The method of the present invention comprises digitally testing the differential driver circuit by activating a test enable signal, skewing the differential output termination impedance in response to the test enable signal, adjusting a voltage offset of the differential receiver circuit in response to the test enable signal, selecting a power level for the differential driver circuit in response to the test enable signal, enabling a decoder in response to the test enable signal, wherein the decoder activates only one segment of the differential driver circuit during any one test sequence, activating one of the segments for testing, stimulating the differential driver circuit with digital test patterns, receiving an output of the differential driver circuit by the differential receiver circuit, converting the received differential driver output to a single-ended signal, observing the single-ended signal; and deactivating the test enable signal.

System, Method And Software Program For Tuneable Equalizer Adaptation Using Sample Interpolation

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US Patent:
20170346662, Nov 30, 2017
Filed:
May 25, 2016
Appl. No.:
15/164162
Inventors:
- Grand Cayman, KY
Matthew B. BAECHER - Rock Tavern NY, US
Assignee:
GLOBALFOUNDRIES INC. - GRAND CAYMAN
International Classification:
H04L 25/03
H04L 7/00
H03M 1/12
Abstract:
Various embodiments of the present invention solve the problem of generating intermediate-time information useable to drive ZFE adaptation (for example, in connection with a digital receiver). Further, various embodiments of the present invention increase flexibility by enabling user-specified over-peaking and/or under-peaking (i.e. configurable equalizer tuning) with respect to a ZFE convergence (or lock) criterion.

On-Chip Test For Integrated Ac Coupling Capacitors

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US Patent:
20150198647, Jul 16, 2015
Filed:
Jan 16, 2014
Appl. No.:
14/156487
Inventors:
- Armonk NY, US
Matthew B. Baecher - Newburgh NY, US
John F. Bulzacchelli - Yonkers NY, US
Stanislav Polonsky - Putnam Valley NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G01R 31/01
G01R 31/28
G01R 1/30
Abstract:
Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.

Testing A Digital-To-Analog Converter

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US Patent:
20150145710, May 28, 2015
Filed:
Nov 26, 2013
Appl. No.:
14/089790
Inventors:
- Armonk NY, US
MATTHEW B. BAECHER - NEWBURGH NY, US
WILLIAM R. KELLY - VERBANK NY, US
JOSEPH F. LOGAN - RALEIGH NC, US
PINPING SUN - FISHKILL NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03M 1/10
H03M 1/66
US Classification:
341120
Abstract:
Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Testing A Decision Feedback Equalizer ('Dfe')

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US Patent:
20150131707, May 14, 2015
Filed:
Jan 19, 2015
Appl. No.:
14/599605
Inventors:
- Armonk NY, US
MATTHEW B. BAECHER - NEWBURGH NY, US
MINHAN CHEN - CARY NC, US
WILLIAM R. KELLY - VERBANK NY, US
TODD M. RASMUS - CARY NC, US
International Classification:
H04L 1/24
H04L 25/03
US Classification:
375224
Abstract:
Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Testing A Decision Feedback Equalizer ('Dfe')

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US Patent:
20140376603, Dec 25, 2014
Filed:
Jun 19, 2013
Appl. No.:
13/921470
Inventors:
- ARMONK NY, US
MATTHEW B. BAECHER - NEWBURGH NY, US
MINHAN CHEN - CARY NC, US
WILLIAM R. KELLY - VERBANK NY, US
TODD M. RASMUS - CARY NC, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY
International Classification:
H04B 17/00
US Classification:
375224
Abstract:
Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
Matthew B Baecher from Rock Tavern, NY, age ~46 Get Report