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Mark D Hoinkis

from Fishkill, NY
Age ~60
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Also known as:
Mark H Hoinkis
Phone and address:
37 Spruce Ridge Dr, Fishkill, NY 12524
(845) 838-6734
Related to:
Timothy S Hoinkis, 54Joseph Timothy Walsh, 61James F Walsh, 72Michael J Mcstravock, 58Samantha J Tartar, 34Grace M McstravockAlex H Tartar, 64Colleen D Mcstravock, 58Joseph M Mcstravock, 64
Connected to:
John E Hoinoski, 58Christopher A Hoinowski, 48Casey M Hoins, 42Susan A Hoins, 61Kyle Hoinville, 49Cheryl Hoiosen, 48Gayla J Hoipkemeier, 69Miki A Hoiriis, 41Jerome R Hoiseth, 77Amanda C Hoisington, 37

Mark Hoinkis Phones & Addresses

  • 37 Spruce Ridge Dr, Fishkill, NY 12524 (845) 838-6734
  • 37 Spruce Ridge Dr APT 14, Fishkill, NY 12524 (845) 838-6734
  • San Jose, CA
  • Raleigh, NC
  • Sunnyvale, CA
  • Yardley, PA
  • Levittown, PA
  • Madison Township, PA
  • Mountain View, CA
  • 37 Spruce Ridge Dr, Fishkill, NY 12524

Work

Company: Applied materials Position: Member of technical staff

Education

Degree: Graduate or professional degree

Industries

Semiconductors

Resumes

Resumes

Mark Hoinkis Photo 1

Member Of Technical Staff

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Location:
37 Spruce Ridge Dr, Fishkill, NY 12524
Industry:
Semiconductors
Work:
Applied Materials
Member of Technical Staff
Applied Materials
Member of Technica Staff

Publications

Us Patents

Copper Vias In Low-K Technology

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US Patent:
6383929, May 7, 2002
Filed:
Jan 11, 2001
Appl. No.:
09/759015
Inventors:
Steven H. Boettcher - Fishkill NY
Herbert L. Ho - Cornwall NY
Mark Hoinkis - Fishkill NY
Hyun Koo Lee - LaGrangeville NY
Yun-Yu Wang - Poughquag NY
Kwong Hon Wong - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk
Infineon Technologies North America Corp. - San Jose CA
International Classification:
H01L 2144
US Classification:
438687, 438643, 438644, 438653, 438654
Abstract:
In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

Chromium Adhesion Layer For Copper Vias In Low-K Technology

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US Patent:
6539625, Apr 1, 2003
Filed:
Jan 11, 2001
Appl. No.:
09/759017
Inventors:
Brett H. Engel - Fishkill NY
Mark Hoinkis - Fishkill NY
John A. Miller - Newburgh NY
Yun-Yu Wang - Poughquag NY
Kwong Hon Wong - Wappingers Falls NY
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies AG - Munich
International Classification:
H05K 302
US Classification:
29846, 29847, 29852, 29830, 29831
Abstract:
In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Cr, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while maintaining low resistance.

Via Density Rules

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US Patent:
6864171, Mar 8, 2005
Filed:
Oct 9, 2003
Appl. No.:
10/682462
Inventors:
Mark D. Hoinkis - Fishkill NY, US
Matthias P. Hierlemann - Hsinchu, TW
Mohammed Fazil Fayaz - Pleasantville NY, US
Andy Cowley - Wappingers Falls NY, US
Erdum Kaltalioglu - Hsinchu, TW
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L021/4763
US Classification:
438638, 257774, 257775, 257776, 738639, 738640, 738668
Abstract:
Thermo-mechanical stress on vias is reduced, thereby reducing related failures. This can be done by maintaining a via-to-metal area ratio at least as large as a predetermined value below which the additional stress on the vias does not significantly increase.

Device Interconnection

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US Patent:
6870263, Mar 22, 2005
Filed:
Mar 31, 1998
Appl. No.:
09/052688
Inventors:
Lawrence A. Clevenger - Lagrangeville NY, US
Ronald G. Filippi - Wappingers Falls NY, US
Mark Hoinkis - Fishkill NY, US
Jeffery L. Hurd - Marlboro NY, US
Roy C. Iggulden - Newburgh NY, US
Herbert Palm - Hoehenkirchen-Siegertsbrunn, DE
Hans W. Poetzlberger - Munich, DE
Kenneth P. Rodbell - Poughquag NY, US
Florian Schnabel - Wappingers Falls NY, US
Stefan Weber - Fishkill NY, US
Ebrahim A. Mehter - Wappingers Falls NY, US
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L023/48
US Classification:
257750, 257767
Abstract:
A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Stress-Relief Layer For Semiconductor Applications

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US Patent:
6960835, Nov 1, 2005
Filed:
Oct 30, 2003
Appl. No.:
10/698057
Inventors:
Hans-Joachim Barth - Munich, DE
Erdem Kaltalioglu - Fishkill NY, US
Mark D. Hoinkis - Fishkill NY, US
Gerald R. Friese - Munich, DE
Pak Leung - Cedar Park TX, US
Assignee:
Infineon Technologies AG - Munich
United Microelectronics Co. - Hsin-Chu
International Classification:
H01L023/48
H01L021/4763
US Classification:
257758, 257635, 438622
Abstract:
In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.

Crystallographic Modification Of Hard Mask Properties

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US Patent:
7001835, Feb 21, 2006
Filed:
Nov 21, 2003
Appl. No.:
10/707119
Inventors:
Lawrence A. Clevenger - LaGrangeville NY, US
Andrew P. Cowley - Wappingers Falls NY, US
Timothy J. Dalton - Ridgefield CT, US
Mark Hoinkis - Fishkill NY, US
Steffen K. Kaldor - Fishkill NY, US
Kaushik A. Kumar - Beacon NY, US
Stephen M. Rossnagel - Pleasantville NY, US
Andrew H. Simon - Fishkill NY, US
Douglas C. La Tulipe, Jr. - Danbury CT, US
Assignee:
International Business Machines Corporation - Armonk NY
Infineon Technologies, AG - Munich
International Classification:
H01L 21/4763
US Classification:
438618, 438637
Abstract:
A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing Nand a flow rate such that (Nflow)/(N+carrier flow)>0. 5.

Bilayered Metal Hardmasks For Use In Dual Damascene Etch Schemes

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US Patent:
7052621, May 30, 2006
Filed:
Jun 13, 2003
Appl. No.:
10/461090
Inventors:
Kaushik Kumar - Beacon NY, US
Lawrence Clevenger - LaGrangeville NY, US
Timothy Dalton - Ridgefield CT, US
Douglas C. La Tulipe - Danbury CT, US
Andy Cowley - Wappingers Falls NY, US
Erdem Kaltalioglu - Hsin-Chu, TW
Jochen Schacht - Hsin-Chu, TW
Andrew H. Simon - Fishkill NY, US
Mark Hoinkis - Fishkill NY, US
Steffen K. Kaldor - Fishkill NY, US
Chih-Chao Yang - Beacon NY, US
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
C23F 1/00
US Classification:
216 51, 438622, 438623, 438627, 438628, 438648, 428336, 428446, 428457, 428627, 428660, 428698
Abstract:
A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

Reduction Of The Shear Stress In Copper Via's In Organic Interlayer Dielectric Material

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US Patent:
7060619, Jun 13, 2006
Filed:
Mar 4, 2003
Appl. No.:
10/379346
Inventors:
Andy Cowley - Wappinger Falls NY, US
Erdem Kaltalioglu - Wappinger Falls NY, US
Mark Hoinkis - Fishkill NY, US
Michael Stetter - Munich, DE
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L 21/44
H01L 21/4763
US Classification:
438687, 438624, 438626, 438627, 438637
Abstract:
Interconnect layers on a semiconductor body containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAMS) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0. 18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of an applied barrier layer, on the recessed copper surfaces, is controlled to become essentially co-planar with the surrounding insulator surfaces. A thicker barrier layer eliminates the need for a capping layer. The elimination of a capping layer results in a reduction in the overall capacitive coupling, stress, and cost.
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Mark D Hoinkis from Fishkill, NY, age ~60 Get Report