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Mark I Himelstein

from Emerald Hills, CA
Age ~64
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Also known as:
Mark Ira Himelstein, Mark Tr Himelstein, Mark Living Himelstein, Mark L Himelstein, Mark J Himelstein, Mark Himelstein Revocable Li, Mark N, Mark Himmelstein
Related to:
Xiaoxia Lu, 54Sandra Himelstein, 90Samantha Himelstein, 33Alan Himelstein, 67Sammi HimelsteinLaurie Himelstein, 67
Connected to:
Arnold M Himelstein, 75Nathan G Himelstein, 87Peggy D Himelstein, 92Robert A Himelstieb, 68Lidia E Himely, 64Christine L Himeno, 62Adina A Himes, 47Angela S Himes, 52Brad L Himes, 40Briana M Himes, 28

Mark Himelstein Phones & Addresses

  • Emerald Hills, CA
  • San Mateo, CA
  • Pacifica, CA
  • 171 N Dawes Ave, Kingston, PA 18704 (570) 288-9293
  • Saratoga, CA
  • San Jose, CA
  • 1573 Edgewood Rd, Emerald Hills, CA 94062 (408) 250-6611

Work

Position: Service Occupations

Education

Degree: Associate degree or higher

Emails

m***[email protected]

Professional Records

Lawyers & Attorneys

Mark Himelstein Photo 1

Mark Himelstein, Berkeley CA - Lawyer

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Office:
1936 University Ave. Ste 355, Berkeley, CA 94704
Admitted:
1968, District of Columbia
1969, California
1972, U.S. Supreme Court
University:
Indiana University, A.B.
George Washington University, LL.B.
Biography:
Mark Himelstein has practiced law in California since 1969. He was involved as a principal in a number of small to medium size law firms in San Francisco, CA, from 1969 to 1994. From 1994 to the prese...

Resumes

Resumes

Mark Himelstein Photo 2

Vice President Of Products At Graphite Systems, Inc.

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Position:
Vice President of Products at Graphite Systems, Inc., President at Heavenstone, Inc.
Location:
San Francisco Bay Area
Industry:
Computer Software
Work:
Graphite Systems, Inc. - Menlo Park, CA since Apr 2012
Vice President of Products
Heavenstone, Inc. - Emerald Hills, CA since Jan 2005
President
Quantum Jan 2010 - Oct 2011
Chief Technology Officer
Infoblox Jan 2004 - Jan 2005
Vice President Engineering
digeo 2002 - 2003
senior vice president of software
Education:
Stanford University Graduate School of Business 2011 - 2011
CTO Program, Strategic Leadership and Innovation University of California, Davis 1981 - 1983
M.S., Computer Science Wilkes University 1977 - 1981
BS, Mathematics, Computer Science
Skills:
SaaS
Management
Cloud Computing
Leadership
Software Development
Enterprise Software
Product Development
Technical Writing
System Architecture
Business Alliances
Infrastructure
Mark Himelstein Photo 3

Attorney At Self Employed

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Position:
Attorney at Self Employed (Self-employed)
Location:
San Francisco Bay Area
Industry:
Law Practice
Work:
Self Employed
Attorney

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mark Himelstein
Chief Financial Officer
Graphite Systems, Inc.
Computer Hardware · Custom Computer Programing
2037 Landings Dr, Mountain View, CA 94043
1883 Landings Dr, Mountain View, CA 94043
1521 California Cir, Milpitas, CA 95035
3175 Hanover St, Palo Alto, CA 94304
Mark Himelstein
Principal
Himelstein Mark Attorney at Law
Legal Services Office
2937 Russell St, Berkeley, CA 94705
Mark Himelstein
President
Heavenstone Inc
Management Consulting
12256 Candy Ct, Saratoga, CA 95070
(408) 250-6611
Mark Himelstein
President
HIMELSOFT, INC
12256 Candy Ct, Saratoga, CA 95070
(408) 255-8227

Publications

Us Patents

System And Method For Obtaining Correct Byte Addresses By Using Logical Operations On 2 Least Significant Bits Of Byte Address To Facilitate Compatibility Between Computer Architectures Having Different Memory Orders

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US Patent:
55727131, Nov 5, 1996
Filed:
Jan 27, 1995
Appl. No.:
8/379710
Inventors:
Larry B. Weber - Palo Alto CA
Earl A. Killian - Los Altos CA
Mark I. Himelstein - San Jose CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 700
US Classification:
395500
Abstract:
A method and computer program-product for converting a program designed to be executed on a computer system employing a first predefined memory order, such as the Big Endian architecture, to a program which is executable on a computer system employing a second predefined memory order, such as the Little Endian architecture. The method and computer program-product uses the fact that performing a logical operation on the lower two bits of a byte address in one architecture converts that byte address to the equivalent byte address in the other architecture. The method and computer program-product are implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and operating on the two least significant bits of the byte address with a logical operation to generate two complementary bits used to replace the two least significant bits of the byte address to generate a new byte address that corresponds with the other architecture.

Object Identification In A Moving Video Image

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US Patent:
62052314, Mar 20, 2001
Filed:
May 10, 1995
Appl. No.:
8/435439
Inventors:
Anthony J. Isadore-Barreca - Oakland CA
David R. Emberson - Santa Cruz CA
Mark I. Himelstein - Saratoga CA
Donald E. Meyer - Cupertion CA
Assignee:
Identive Corporation - San Jose CA
International Classification:
G06K 900
US Classification:
382103
Abstract:
A moving object identification method (10) for identifying and tracing an object (20) within a video image (14) such that the object (20) can act as a hot spot (30) as for an interactive computer/user interface (70). A plurality of tags (28) define the edges (26) of the object (20) and a plurality of hot spot borders (32) define the hot spot (30) such that the hot spot (30) and the object (20) generally coincide. A physical tag (28b) is optionally used to position the tags (28). Sensitivity to disappearance of the edges (26) is adjustable according to the relative size of a subtag (68) to the corresponding tag (28).

System For Obtaining Correct Byte Addresses By Xor-Ing 2 Lsb Bits Of Byte Address With Binary 3 To Facilitate Compatibility Between Computer Architecture Having Different Memory Orders

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US Patent:
53983289, Mar 14, 1995
Filed:
Sep 27, 1983
Appl. No.:
8/127105
Inventors:
Larry B. Weber - Palo Alto CA
Earl A. Killian - Los Altos CA
Mark I. Himelstein - San Jose CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 700
US Classification:
395500
Abstract:
A method and apparatus for enabling a computer to run using either a Big Endian or Little Endian architecture is provided. The method and apparatus use the fact that XORing the lower two bits of a byte address in one architecture with a binary 3 converts that byte address to the equivalent byte address in the other architecture. The conversion method and apparatus is implemented in hardware by setting a bit in a status register indicating a Big Endian or Little Endian architecture in conjunction with an XOR gate which couples the byte address to binary 3. The conversion method and apparatus is implemented in software by scanning the instructions of the input for load and store instructions. The software modifies the instructions by taking the contents of the register and XORing the two least significant bits of the byte address with a binary 3.

Multiprocessor System With Independent Direct Access To Bulk Solid State Memory Resources

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US Patent:
20170076763, Mar 16, 2017
Filed:
Nov 3, 2016
Appl. No.:
15/342940
Inventors:
- Hopkinton MA, US
Mark Himelstein - Emerald Hills CA, US
Bruce Wilford - Los Altos CA, US
Dan Arai - Sunnyvale CA, US
David R. Emberson - Santa Cruz CA, US
International Classification:
G11C 7/10
G06F 15/173
G06F 15/167
Abstract:
A system includes a plurality of processors, each being coupled to each of remaining processors via a cluster of processor interconnects. The cluster of processor interconnects form a data distribution network. The system further includes a plurality of roots coupled to the processors, each root corresponding to one of the processors. Each root comprises a memory controller, one or more branches coupled to the memory controller, and a plurality of memory leaves coupled to the branches, each memory leaf having one or more solid state memory devices. Each of the branches is associated with one or more of the memory leaves and provides access to the associated memory leaves. Each of the processors can access any one of the memory leaves via a corresponding branch of any one of the roots over the data distribution network.
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Mark I Himelstein from Emerald Hills, CA, age ~64 Get Report