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Mark D Hennecke

from Cupertino, CA
Age ~60

Mark Hennecke Phones & Addresses

  • 10870 Stelling Rd, Cupertino, CA 95014 (408) 252-4803
  • 20800 Homestead Rd APT 45D, Cupertino, CA 95014 (408) 252-4803
  • 20800 Homestead Rd APT 65B, Cupertino, CA 95014

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Skills

Distributed Systems • Debugging • Processors • Software Engineering • Scalability • Linux • Computer Architecture • X86 • Embedded Systems • Device Drivers • C • Software Development

Languages

English

Industries

Computer Software

Resumes

Resumes

Mark Hennecke Photo 1

Mark Hennecke

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Location:
20800 Homestead Rd, Cupertino, CA 95014
Industry:
Computer Software
Skills:
Distributed Systems
Debugging
Processors
Software Engineering
Scalability
Linux
Computer Architecture
X86
Embedded Systems
Device Drivers
C
Software Development
Languages:
English

Publications

Us Patents

Systems And Methods For Control Of Integrated Circuits Comprising Body Biasing Systems

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US Patent:
7509504, Mar 24, 2009
Filed:
Sep 30, 2004
Appl. No.:
10/956219
Inventors:
Kleanthes G. Koniaris - Palo Alto CA, US
Stephen Lee - Los Altos CA, US
Mark Hennecke - Cupertino CA, US
Assignee:
Transmeta Corporation - Santa Clara CA
International Classification:
G06F 1/26
US Classification:
713300, 327537
Abstract:
Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.

Dynamic Chip Control

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US Patent:
7917772, Mar 29, 2011
Filed:
Sep 29, 2006
Appl. No.:
11/529865
Inventors:
Kleanthes G. Koniaris - Palo Alto CA, US
James B. Burr - Foster City CA, US
Mark Hennecke - Cupertino CA, US
International Classification:
G06F 1/00
US Classification:
713300
Abstract:
Methods and systems for operating a semiconductor device (e. g. , a microprocessor) are described. The microprocessor is initially operated at a voltage and frequency that would be within operating limits at any device temperature. Using models that relate device temperature, operating limits and power consumption with voltage and frequency, the amount of supply voltage and a new operating frequency can be selected. The models are periodically consulted thereafter to continue adjusting the supply voltage and operating frequency, so that the microprocessor is caused to operate at very close to its capacity, in particular in those instances when, for example, processor-intensive instructions are being executed.

Systems And Methods For Control Of Integrated Circuits Comprising Body Biasing Systems

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US Patent:
8127156, Feb 28, 2012
Filed:
Mar 24, 2009
Appl. No.:
12/410249
Inventors:
Kleanthes G. Koniaris - Palo Alto CA, US
Stephen Lee - Los Altos CA, US
Mark Hennecke - Cupertino CA, US
International Classification:
G06F 1/26
US Classification:
713300, 327537
Abstract:
Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.

Systems And Methods For Control Of Integrated Circuits Comprising Body Biasing Systems

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US Patent:
8458496, Jun 4, 2013
Filed:
Feb 27, 2012
Appl. No.:
13/406434
Inventors:
Kleanthes G. Koniaris - Palo Alto CA, US
Stephen Lee - Los Altos CA, US
Mark Hennecke - Cupertino CA, US
International Classification:
G06F 1/26
US Classification:
713300, 713320, 327537
Abstract:
Systems and methods for control of integrated circuits comprising body-biasing systems. In accordance with a first embodiment of the present invention, a desirable power condition of a computer system comprising a microprocessor is determined. Body biasing voltage information corresponding to the power condition is accessed. A voltage supply coupled to a body terminal of the microprocessor is commanded to generate a voltage corresponding to the body biasing voltage information corresponding to the power condition.

Dynamic Chip Control

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US Patent:
20110296208, Dec 1, 2011
Filed:
Feb 28, 2011
Appl. No.:
13/037042
Inventors:
Kleanthes G. Koniaris - Palo Alto CA, US
James B. Burr - Foster City CA, US
Mark Hennecke - Cupertino CA, US
International Classification:
G06F 1/00
US Classification:
713300
Abstract:
Methods and systems for operating a semiconductor device (e.g., a microprocessor) are described. The microprocessor is initially operated at a voltage and frequency that would be within operating limits at any device temperature. Using models that relate device temperature, operating limits and power consumption with voltage and frequency, the amount of supply voltage and a new operating frequency can be selected. The models are periodically consulted thereafter to continue adjusting the supply voltage and operating frequency, so that the microprocessor is caused to operate at very close to its capacity, in particular in those instances when, for example, processor-intensive instructions are being executed.

Power Allotment Distribution In A Data Center

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US Patent:
20120078430, Mar 29, 2012
Filed:
Sep 28, 2010
Appl. No.:
12/892116
Inventors:
Xiaobo Fan - Sunnyvale CA, US
Chris Sadler - Mountain View CA, US
Selver Corhodzic - Santa Clara CA, US
Wolf-Dietrich Weber - San Jose CA, US
Taliver Brooks Heath - Mountain View CA, US
Mark Hennecke - Cupertino CA, US
International Classification:
G06F 1/26
US Classification:
700295
Abstract:
In a computer-implemented method, an electronic communication from a first computing machine is received and includes a power value and one or more priority values. The power value represents a request for a power allotment expected to be used during a predetermined time and the priority values represent priorities of tasks expected to be executed during the predetermined time. A score for the request is calculated using a scoring function and the received priority values as inputs to the scoring function. The score is compared to one or more other scores respectively associated with requests for power allotments from other computing machines and previously calculated using the scoring function following receipt of one or more electronic communications each including a power value and one or more priority values. A top-ranked score is identified and an electronic communication is sent to the associated computing machine granting the requested power allotment.

Method And Apparatus For Pre-Allocation Of System Resources To Facilitate Garbage Collection

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US Patent:
6446257, Sep 3, 2002
Filed:
Feb 4, 1999
Appl. No.:
09/244320
Inventors:
Salil Pradhan - Santa Clara CA
Mark D. Hennecke - Cupertino CA
Michey N Mehta - San Jose CA
Ruslan Meshenberg - Santa Clara CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F71701
US Classification:
717154, 707206
Abstract:
A generational garbage collection tool and method for a computer system that pre-allocates computer resources during compile-time for later use by a generational garbage collector at run-time. The invention reduces the overall cost of dealing with long-lived objects and thereby allows a generational garbage collector to focus deallocation efforts on young objects, which are more likely to be dead. The present embodiment reduces pause time to a level that does not disturb interactive users. The embodiment allocates space for interior pointers at compile-time when the location of interior pointers is known and thereby facilitates generational garbage collection. By enabling the use of threaded interior pointers during generational garbage collection, live object relocation is improved by requiring an update to one pointer instead of updating each pointer that references an object. The present embodiment identifies the pointers that may be updated due to generational garbage collection, and by selectively allocating space to only those pointers that may be accessed during generational garbage collection and not all pointers, computer resources are saved. Further, the present embodiment may include locking information in the pointer to determine whether the object is presently being updated and is therefore locked.
Mark D Hennecke from Cupertino, CA, age ~60 Get Report