Mark D Hahm

6378106, Apr 23, 2002

May 28, 1999

09/321794

Stephan A. Allpress - Hoboken NJ
Mark D. Hahm - Flanders NJ

Lucent Technologies Inc. - Murray Hill NJ

H03M 1300

714795

A recursive, single-wrong-turn (SWT) decoding method and Viterbi decoder which requires no additional circuitry or processing to keep track of a running list of the L best paths. If the most likely (ML) path fails frame quality metric tests, a search is made through a trellis using an existing survivor (trace back) information stored in a survivor (trace back) memory. An iteration in the recursive algorithm includes tracing back along the ML path to a particular stage, then deviating from the ML path and following the survivor information along that new deviant path, and finally checking the fully decoded frame to see if the frame quality metrics are acceptable for the frame. These same trace back steps can be performed for every stage in the trellis, deviating from a different stage on the ML path each time. A recursive, single-wrong-turn (SWT) decoding method and Viterbi decoder which exceed the performance of the general Viterbi algorithm and the various conventional list Viterbi decoders and which is much less computationally and physical complex.

7342979, Mar 11, 2008

Mar 3, 2004

10/791945

Li Fung Chang - Holmdel NJ, US
Mark D. Hahm - Hartland WI, US

Broadcom Corporation - Irvine CA

H03K 9/00

375316

A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, a plurality of IR processing module registers, and an IR processing module. The baseband processor receives an analog signal and produces samples. The equalizer is operable to receive the samples, to equalize the samples, and to produce soft decision bits corresponding to the data block. The system processor receives the soft decision bits of the data block, configures the plurality of IR processing module registers, and initiates operations of the IR processing module. The IR processing module accesses the plurality of IR processing module registers, receives the soft decision bits of the data block, and performs IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block.

7515601, Apr 7, 2009

May 31, 2005

11/140805

Jie Lai - Belle Mead NJ, US
Mark David Hahm - Hartland WI, US

Broadcom Corporation - Irvine CA

H04B 7/212

370442, 370479, 375265, 714792

A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric performs error detection operations, and extracts information from a MAC packet that it produces.

7532638, May 12, 2009

Jun 1, 2005

11/142213

Mark David Hahm - Hartland WI, US
Li Fung Chang - Holmdel NJ, US
Michiel Lotter - San Diego CA, US

Broadcom Corporation - Irvine CA

H04B 7/212

370442, 370479, 375265, 714792

A baseband processing module for use within a Radio Frequency (RF) transceiver includes a downlink/uplink interface, TX processing components, a processor, memory, RX processing components, and a turbo decoding module. The RX processing components receive a baseband RX signal from the RF front end, produce a set of IR samples from the baseband RX signal, and transfer the set of IR samples to the memory. The turbo decoding module receives at least one set of IR samples from the memory, forms a turbo code word from the at least one set of IR samples, turbo decodes the turbo code word to produce inbound data, and outputs the inbound data to the downlink/uplink interface. The turbo decoding module performs metric normalization based upon a chosen metric, performs de-rate matching, performs error detection operations, and extracts information from a MAC packet that it produces.

7620099, Nov 17, 2009

Aug 31, 2005

11/216449

Mark David Hahm - Hartland WI, US
Baoguo Yang - San Jose CA, US

Broadcom Corporation - Irvine CA

H04B 1/00

375150, 375142, 375144, 375147, 375148, 375149, 375316, 375317, 375324, 375325, 375349

A baseband processing module according to the present invention includes a multi-path scanner module. The multi-path scanner module is operable to receive timing and scrambling code information regarding an expected multi-path signal component of a WCDMA signal. Then, the multi-path scanner module is operable to identify a plurality of multi-path signal components of the WCDMA signal by descrambling, despreading and correlating a known symbol pattern of/with a baseband RX signal within a search window. The multi-path scanner module is operable to determine timing information for the plurality of multi-path signal components of the WCDMA signal found within the search window and to pass this information to a coupled rake receiver combiner module.

7668188, Feb 23, 2010

Feb 14, 2006

11/353886

Li Fung Chang - Holmdel NJ, US
Mark Hahm - Hartland WI, US
Simon Baker - San Diego CA, US

H04L 12/28
H04L 12/56

370415

Methods and systems for processing signals in a communication system are disclosed and may include pipelining processing of a received HSDPA bitstream within a single chip. The pipelining may include calculating a memory address for a current portion of a plurality of information bits in the received HSDPA bitstream, while simultaneously storing on-chip, a portion of the plurality of information bits in the received bitstream that is subsequent to the current portion. A portion of the plurality of information bits in the received HSDPA bitstream that is previous to the current portion may be decoded during the calculating and the storing. The calculation of the memory address for the current portion of the plurality of information bits may be achieved without the use of a buffer. Processing of the plurality of information bits may be partitioned into a functional data processing path and a functional address processing path.

7680083, Mar 16, 2010

Sep 6, 2005

11/221072

Mark David Hahm - Hartland WI, US
Huaiyu (Hanks) Zeng - Red Bank NJ, US
Joseph Boccuzzi - Manalapan NJ, US
Nelson R. Sollenberger - Farmingdale NJ, US

Broadcom Corporation - Irvine CA

H04B 7/216
H04B 1/00

370335, 375148

A baseband processing module includes an RX interface, a rake receiver combiner module, and may include additional components. The RX interface receives the baseband signals from an RF front end and creates baseband RX signal samples there from. The rake receiver combiner module includes control logic, an input buffer, a rake despreader module, and an output buffer. The rake despreader module is operable to despread the baseband RX signal samples in a time divided fashion to produce channel symbols including pilot channel symbols and physical channel symbols.

7684526, Mar 23, 2010

Sep 21, 2006

11/524584

Junqiang Li - Matawan NJ, US
Mark David Hahm - Hartland WI, US
Nelson R. Sollenberger - Farmingdale NJ, US
Li Fung Chang - Holmdel NJ, US

Broadcom Corporation - Irvine CA

H04B 7/10

375347, 375229

A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.