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Mark Buer Phones & Addresses

  • 570 N Tonto Rim Loop, Payson, AZ 85541 (928) 478-4456
  • Kandiyohi, MN
  • Fountain Hills, AZ
  • 1027 Betsy Ln, Gilbert, AZ 85296 (480) 812-9183
  • Chandler, AZ
  • Maricopa, AZ
  • Andover, MN
  • 570 N Tonto Rim Loop, Payson, AZ 85541 (480) 812-9183

Work

Company: Broadcom Nov 2004 Position: Technical director

Education

Degree: BSEE School / High School: University of Minnesota-Twin Cities 1987 to 1991 Specialities: Engineering

Skills

Semiconductors • Asic • Soc • Ic • Embedded Systems • Mixed Signal • Processors • Wireless • System Architecture • Firmware • Embedded Software • Verilog • Eda • Product Development

Industries

Semiconductors

Resumes

Resumes

Mark Buer Photo 1

Senior Director

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Broadcom since Nov 2004
Technical Director

VLSI Technology 1992 - 2000
Senior Principle Engineer
Education:
University of Minnesota-Twin Cities 1987 - 1991
BSEE, Engineering
Skills:
Semiconductors
Asic
Soc
Ic
Embedded Systems
Mixed Signal
Processors
Wireless
System Architecture
Firmware
Embedded Software
Verilog
Eda
Product Development

Publications

Us Patents

Efficient Hardware Implementation Of A Compression Algorithm

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US Patent:
6348881, Feb 19, 2002
Filed:
Aug 29, 2000
Appl. No.:
09/650693
Inventors:
Mark Leonard Buer - Gilbert AZ
Assignee:
Philips Electronics No. America Corp. - New York NY
International Classification:
H03M 738
US Classification:
341 51, 341 50, 341 60, 341 59, 341 65, 341 87, 341 95, 341106, 375240
Abstract:
Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND between a current value of the match signal currently produced by the memory for the input address data with a prior value of the match signal produced by an immediately prior input address data. A buffer holds index data. A second logic AND function compares output of the first logic AND function with the index data. Output of the second logic AND function is returned to the buffer as new index data. Index logic generates an offset based on the index data stored in the buffer. A send byte function asserts a send byte signal when the match signal is zero and when the output of the second logic AND function is zero. A length counter is incremented for every cycle in which the send byte signal is not asserted.

Secure Cache For Instruction And Data Protection

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US Patent:
6523118, Feb 18, 2003
Filed:
Jun 29, 1998
Appl. No.:
09/106717
Inventors:
Mark Leonard Buer - Gilbert AZ
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
H04L 932
US Classification:
713189, 713187, 713190, 713192, 713193, 713194, 380 28
Abstract:
A computing system, includes a processor, a cache, a memory system, and a secure cache controller system. The cache stores a plurality of cache lines. The memory system stores a plurality of blocks of encrypted data. The secure cache controller system is situated between the memory system and the cache. When there is a miss of a first cache line of data in the cache and the first cache line of data resides in a first block of encrypted data within the memory system, the secure cache controller system fetches the first block of encrypted data, decrypts the first block of encrypted data and forwards the first cache line to the cache.

Integration Of Security Modules On An Integrated Circuit

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US Patent:
6553496, Apr 22, 2003
Filed:
Feb 1, 1999
Appl. No.:
09/241176
Inventors:
Mark Leonard Buer - Gilbert AZ
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
G06F 100
US Classification:
713200, 713202, 713300, 713323, 713340, 702 64, 702190, 714 10, 714 47, 714 55, 714 22, 327 18, 327 39
Abstract:
An integrated circuit includes secure logic that requires protection. Secure assurance logic protects the secure logic. The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions. Each protection module monitors a different type of insecure condition. Each protection module asserts an alarm signal when an associated insecure condition is detected. The alarm signals asserted by the plurality of protection modules are stored.

System And Method For Programming Non-Volatile Memory

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US Patent:
6789159, Sep 7, 2004
Filed:
May 8, 2002
Appl. No.:
10/141599
Inventors:
Jeffrey Douglas Carr - San Diego CA
Mark Buer - Gilbert AZ
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 1200
US Classification:
711103, 711152, 711163, 36518533, 710 14
Abstract:
Systems and methods that may program a non-volatile memory for use in configuring features of a device, such as a set top box, for example, are disclosed. One method may include the steps of beginning a programming cycle; programming mode control bits of the non-volatile memory that correspond to configurations of features of the device; if an interruption occurs during the programming cycle, then rendering the non-volatile memory invalid; and if no interruption occurs during the programming cycle, then rendering the non-volatile memory operational.

Secure Memory Management Unit Which Uses Multiple Cryptographic Algorithms

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US Patent:
6910094, Jun 21, 2005
Filed:
Nov 5, 1998
Appl. No.:
09/186546
Inventors:
Gregory Clayton Eslinger - Phoenix AZ, US
Mark Leonard Buer - Chandler AZ, US
Assignee:
Koninklijke Philips Electronics N.V. - Eindhoven
International Classification:
G06F012/00
US Classification:
711 5, 711164, 713189, 713190
Abstract:
An integrated circuit accesses first encrypted data stored in an external random access memory and accesses second encrypted data stored in an external read-only memory. The external random access memory and the external read-only memory are external to the integrated circuit. When accessing a first portion of the first encrypted data stored in the external random access memory, a first algorithm is used to decrypt the first portion of the first encrypted data. When accessing a first portion of the second encrypted data stored in the external read-only memory, a second algorithm is used to decrypt the first portion of the second encrypted data. The second algorithm is different than the first algorithm.

Methods And Apparatus For Accelerating Secure Session Processing

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US Patent:
7007163, Feb 28, 2006
Filed:
May 31, 2002
Appl. No.:
10/160143
Inventors:
Joseph Tardo - Palo Alto CA, US
Mark Buer - Gilbert AZ, US
Jianjun Luo - Sunnyvale CA, US
Don Matthews - Morgan Hill CA, US
Zheng Qi - Milpitas CA, US
Ronald Squires - Castro Valley CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G06F 11/30
US Classification:
713164, 713168, 713151, 713200, 713201
Abstract:
Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Methods And Apparatus For Accelerating Secure Session Processing

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US Patent:
7134014, Nov 7, 2006
Filed:
Nov 23, 2005
Appl. No.:
11/286111
Inventors:
Joseph Tardo - Palo Alto CA, US
Mark Buer - Gilbert AZ, US
Jianjun Luo - Sunnyvale CA, US
Don Matthews - Morgan Hill CA, US
Zheng Qi - Milpitas CA, US
Ronald Squires - Castro Valley CA, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04L 9/00
US Classification:
713164, 713168, 713151
Abstract:
Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Methods And Apparatus For Implementing A Cryptography Engine

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US Patent:
7142671, Nov 28, 2006
Filed:
Jun 26, 2001
Appl. No.:
09/892240
Inventors:
Zheng Qi - Milpitas CA, US
Mark Buer - Gilbert AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04K 1/00
US Classification:
380 29, 380 28, 380 30, 380 36, 380 37
Abstract:
Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine can be decoupled from surrounding logic by using asynchronous buffers. Bit-sliced design can be implemented by moving expansion and permutation logic out of the timing critical data path. An XOR function can be decomposed into functions that can be implemented more efficiently. A two-level multiplexer can be used to preserve a clock cycle during cryptography processing. Key scheduling can be pipelined to allow efficient round key generation.
Mark L Buer from Payson, AZ, age ~56 Get Report