Mark O Bagula

7339216, Mar 4, 2008

Nov 22, 2005

11/285470

Richard F. Lyon - Los Altos CA, US
Paul M. Hubel - Mountain View CA, US
Mark O. Bagula - Morgan Hill CA, US
Richard B. Merrill - Woodside CA, US

Foveon, Inc. - Santa Clara CA

H01L 31/00

257291, 257440, 257443, 257E27134

An array of vertical color filter (VCF) sensor groups, optionally including or coupled to circuitry for converting photogenerated carriers produced in the sensors to electrical signals, and methods for reading out any embodiment of the array. The array has a top layer (including the top sensors of the sensor group) and at least one low layer including other ones of the sensors. Only the top layer can be read out with full resolution. Each low layer can only be read out with less than full resolution to generate fewer sensor output values than the total number of pixel sensor locations. Typically, the sensor groups are arranged in cells, each cell including a S sensor groups (e. g. , S=4), with S sensors in the top layer and fewer than S sensors in each low layer of the cell. Typically, each cell includes at least one shared sensor (a sensor shared by two or more VCF sensor groups) in each low layer, and each cell includes sensor selection switches (e. g. , transistors) between the cell's sensors and a sense node.

46226303, Nov 11, 1986

Oct 28, 1983

6/546514

Chandra R. Vora - Northboro MA
Michael L. Ziegler - Whitinsville MA
Mark Bagula - Morgan Hill CA
Steve Hamilton - Los Gatos CA

Data General Corporation - Westboro MA

G06F 900

364134

In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.