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Mark Aaldering Phones & Addresses

  • Roseville, CA
  • Albuquerque, NM
  • Sunnyvale, CA
  • Los Gatos, CA
  • San Jose, CA
  • Placitas, NM
  • Santa Clara, CA

Work

Company: Rohm semiconductor Aug 2013 to Oct 2015 Position: Senior director technical product marketing

Education

School / High School: University of Southern California Specialities: Electrical Engineering

Skills

Semiconductors • Fpga • Microprocessors • Operating Systems • Executive Management • Embedded Systems • Engineering Management • Semiconductor Industry • Embedded Software • Ic • Soc • Customer Engagement • Hardware Architecture • Product Marketing • Programmable Logic • Xilinx • Processors • Electronics • Eda • Field Applications • System Design • Product Management • Strategy • Team Management • Program Development • Project Management • Debugging • Field Programmable Gate Arrays • System on A Chip • Integrated Circuits

Industries

Semiconductors

Resumes

Resumes

Mark Aaldering Photo 1

Csun

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Location:
16712 Chirco Dr, Los Gatos, CA 95032
Industry:
Semiconductors
Work:
Rohm Semiconductor Aug 2013 - Oct 2015
Senior Director Technical Product Marketing

Xilinx Jul 2008 - Aug 2012
Vice President - Applications, Boards, Software Verification

Xilinx Jun 2009 - Jul 2012
Vice President and Account Executive For Nec

Xilinx Jul 2000 - Jun 2008
Vice President - Embedded Processing Division

Xilinx Nov 1999 - Dec 2006
Senior Director - Ip Cores Solutions Division
Education:
University of Southern California
California State University, Northridge
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Semiconductors
Fpga
Microprocessors
Operating Systems
Executive Management
Embedded Systems
Engineering Management
Semiconductor Industry
Embedded Software
Ic
Soc
Customer Engagement
Hardware Architecture
Product Marketing
Programmable Logic
Xilinx
Processors
Electronics
Eda
Field Applications
System Design
Product Management
Strategy
Team Management
Program Development
Project Management
Debugging
Field Programmable Gate Arrays
System on A Chip
Integrated Circuits

Publications

Us Patents

Programmable Logic Device With Versatile Exclusive Or Architecture

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US Patent:
60694882, May 30, 2000
Filed:
Nov 14, 1997
Appl. No.:
8/970997
Inventors:
Mark Merrill Aaldering - San Jose CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19177
US Classification:
326 39
Abstract:
A programmable logic device (PLD) includes a fixed EXCLUSIVE OR gate and a programmable logic array (PLA). The PLA includes a plurality of AND gate and a plurality of OR gates, the output of each AND gate being programmably connected to an input of each of the plurality of OR gates. The output of one of the OR gates of the PLA array is fed to one of the inputs of the fixed EXCLUSIVE OR. Since the output of each of the AND gates is available to each of the OR gates in the PLA array, implementation of the EXCLUSIVE OR function is facilitated and the number of product terms (AND gates) required is reduced as compared to known PLDs. The output of a programmable array logic (PAL) array having a plurality of AND gates non-programmably connected to an OR gate is connected to the other one of the inputs of the fixed EXCLUSIVE OR gate. Very wide EXCLUSIVE OR functions are readily implemented using a plurality of identical logic cells having the above architecture, each of which generate an intermediate result which is fed to a final logic cell implementing a wide EXCLUSIVE OR of the intermediate results.
Mark M Aaldering from Roseville, CA, age ~65 Get Report