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Marcus M Poplawski

from Minneapolis, MN
Age ~48
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Also known as:
Marcus G Poplawski
Related to:
Linda A Kenyon, 64Kimberly A Constance, 47Ida Erickson, 83Ellie Poplawski, 25Joyce Onosko, 62Sharon L Phillips, 76Sharon Hough, 62
Connected to:
Agnieszka Poplawska, 52Alice Poplawski, 104Amy K Poplawski, 51Arthur S Poplawski, 46Charlotte Poplawski, 33Daniel P Poplawski, 48Deborah A Poplawsky, 74Dihanna Poplawski, 39Gina L Poplawsky, 34Holly Poplawski, 45

Marcus Poplawski Phones & Addresses

  • Minneapolis, MN
  • Stewartville, MN
  • Presque Isle, WI
  • Rochester, MN
  • Viola, WI
  • 5049 Morgan Ave S, Minneapolis, MN 55419

Work

Company: Micron technology Sep 2011 Address: Greater Minneapolis-St. Paul Area Position: Staff physical design engineer

Education

Degree: BSEE School / High School: University of Minnesota, Twin Cities Sep 1994 to Aug 1998 Specialities: Electrical Engineering

Skills

Asic • Perl • Tcl • Static Timing Analysis • Soc • Physical Verification • Primetime • Debugging • Cadence Virtuoso • Cadence • Physical Design • Eda • Synopsys Tools • Ic • Vlsi • C • Cmos • Timing • Semiconductors • Scripting • Timing Closure • Firmware • Magma • Verilog • Simulations • Vhdl

Industries

Semiconductors

Resumes

Resumes

Marcus Poplawski Photo 1

Ic Chip Integration Engineer At Ibm

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Location:
Minneapolis, MN
Industry:
Semiconductors
Work:
Micron Technology - Greater Minneapolis-St. Paul Area since Sep 2011
Staff Physical Design Engineer
IBM Apr 2010 - Sep 2011
Staff Design Automation Engineer
Toshiba May 2002 - Apr 2010
Staff Design Engineer & Embedded Software Designer
LSI Logic Feb 2000 - May 2002
Physical Design Engineer
IBM Sep 1998 - Feb 2000
Transistor Level Timing Support and Development Engineer
Education:
University of Minnesota, Twin Cities Sep 1994 - Aug 1998
BSEE, Electrical Engineering
Skills:
Asic
Perl
Tcl
Static Timing Analysis
Soc
Physical Verification
Primetime
Debugging
Cadence Virtuoso
Cadence
Physical Design
Eda
Synopsys Tools
Ic
Vlsi
C
Cmos
Timing
Semiconductors
Scripting
Timing Closure
Firmware
Magma
Verilog
Simulations
Vhdl

Publications

Us Patents

Interactive Client-Server Environment For Performing Collaborative Timing Analysis Of Circuit Designs

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US Patent:
6643683, Nov 4, 2003
Filed:
May 8, 2000
Appl. No.:
09/566869
Inventors:
Anthony DeGroff Drumm - Rochester MN
Mark S Fredrickson - Rochester MN
Marcus Matthew Poplawski - Minneapolis MN
Brian Christopher Wilson - Oronoco MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1516
US Classification:
709203, 709224, 709225, 709235, 709217, 709218, 717100, 717104, 716 4, 716 5, 716 6, 703 19
Abstract:
An apparatus, program product and method utilize an interactive request server program to interface a plurality of client computers with a timing analysis program. The interactive request server program receives client requests from the plurality of client computers over a network, and, in response to each client request, accesses the timing analysis program to retrieve timing data based upon such client request and thereafter forwards the timing data to the client computer making such request. The interactive request server program may optionally be implemented using a web server program and an application server program, with the web server program interfacing with the client computers via an Internet-type interface, and the application server program interfacing with the timing analysis program using a programmatic interface supported by the timing analysis program. The web server, program and the application server program interface with one another through the use of scripts, which are executed by the web server in response to client requests, and which generate one or more commands that are issued to the application server program to control the timing analysis program via the programmatic interface.
Control profile
Marcus M Poplawski from Minneapolis, MN, age ~48 Get Report