Inventors:
Marc J. Loinaz - Westfield NJ
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H03K 1762
Abstract:
A unique hierarchical multiplexer is employed to multiplex signals read out from analog array elements one at a time to an output. In an embodiment of the invention, the multiplexer switching elements, i. e. , switches, are arranged in groups in a hierarchical, i. e. , tree, configuration. In the tree configuration for a given analog array size, output capacitance is significantly reduced because each analog array element and its associated buffer amplifier drive fewer switches than in other configurations. The lower capacitance reduces any resulting FPN and the resulting lower analog array element and buffer amplifier drive current reduces power dissipation. The reduced capacitance also decreases the transient settling time interval. In one embodiment of the invention, a hierarchical multiplexer employed in reading out signals from elements of an analog array is optimized to produce low FPN by employing unity gain buffer amplifiers which are associated on a one-to-one basis with the analog array elements; using offset correction to compensate for nonuniformity of offset voltages or currents among the buffer amplifiers; not allowing direct current (DC) to flow in switches utilized in the multiplexer; and allowing all transients to settle prior to reading out signals from the analog array elements. In a specific embodiment of the invention, the offset compensation is effected for signals being read out from each element of the analog array by sampling and storing a first value representative of a âregularâ output from the multiplexer that is associated with a particular array element and its associated buffer amplifier, sampling and storing a second value representative of a reference output, i. e.