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Marc Loinaz Phones & Addresses

  • Los Altos Hills, CA
  • New York, NY
  • 4177 Briarwood Way, Palo Alto, CA 94306 (650) 843-1078
  • 230 Davenport Way, Palo Alto, CA 94306 (650) 843-1078
  • Warren Way, Palo Alto, CA 94301
  • 281 Canterbury Rd, Westfield, NJ 07090 (908) 928-0117
  • Holmdel, NJ
  • Santa Clara, CA
  • 12660 Corte Madera Ln, Los Altos Hills, CA 94022 (650) 387-2826

Work

Position: Sales Occupations

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Marc Loinaz
Executive Director
Burriss and Monahan
Other Computer Related Services
201 San Antonio Cir STE 160, Mountain View, CA 94040
(650) 948-7127

Publications

Us Patents

Analog-To-Digital Converter Having Voltage To-Time Converter And Time Digitizer, And Method For Using Same

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US Patent:
6346907, Feb 12, 2002
Filed:
Mar 5, 1999
Appl. No.:
09/263173
Inventors:
Susan M. Dacy - New Port Richey FL
Marc J. Loinaz - Westfield NJ
Assignee:
Agere Systems Guardian Corp. - Miami Lakes FL
International Classification:
H03M 156
US Classification:
341169, 341157
Abstract:
A single slope A/D converter utilizes a sub-nanosecond time digitizer to achieve increased conversion rates independent of a high frequency clock, and so is capable of being implemented in diverse applications. High conversion rates ranging from about 3 MHz to about 12 MHz and higher may be implemented on integrated circuits without using a high frequency clock.

Loss-Of-Signal Detector For Clock/Data Recovery Circuits

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US Patent:
6377082, Apr 23, 2002
Filed:
Aug 17, 2000
Appl. No.:
09/641158
Inventors:
Marc J. Loinaz - Westfield NJ
Gary D. Polhemus - Sebago ME
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H03K 522
US Classification:
327 20, 327 24, 327156
Abstract:
A loss-of-signal (LOS) detector, for example, for a clock/data recovery (CDR) circuit for an optical fiber communication system, has (1) a transition detector for detecting stuck-on-one and stuck-on-zero LOS conditions and (2) an inconsistency detector for detecting other types of LOS conditions. In one embodiment, the inconsistency detector has two decision circuits having different operating conditions (e. g. , different decision thresholds and/or different sampling times). The two decision circuits are configured to generate like output signals (i. e. , both high or both low), when a valid input data signal is applied. However, at certain times during certain LOS conditions, the outputs of the two decision circuits will be mutually inconsistent (i. e. , one high and one low). If the number of such inconsistencies over a specified time period exceeds a specified threshold level, then an LOS condition is determined.

Hierarchical Multiplexer For Analog Array Readout

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US Patent:
6417717, Jul 9, 2002
Filed:
Dec 31, 1998
Appl. No.:
09/223874
Inventors:
Marc J. Loinaz - Westfield NJ
Assignee:
Agere Systems Guardian Corp. - Orlando FL
International Classification:
H03K 1762
US Classification:
327407, 327 99
Abstract:
A unique hierarchical multiplexer is employed to multiplex signals read out from analog array elements one at a time to an output. In an embodiment of the invention, the multiplexer switching elements, i. e. , switches, are arranged in groups in a hierarchical, i. e. , tree, configuration. In the tree configuration for a given analog array size, output capacitance is significantly reduced because each analog array element and its associated buffer amplifier drive fewer switches than in other configurations. The lower capacitance reduces any resulting FPN and the resulting lower analog array element and buffer amplifier drive current reduces power dissipation. The reduced capacitance also decreases the transient settling time interval. In one embodiment of the invention, a hierarchical multiplexer employed in reading out signals from elements of an analog array is optimized to produce low FPN by employing unity gain buffer amplifiers which are associated on a one-to-one basis with the analog array elements; using offset correction to compensate for nonuniformity of offset voltages or currents among the buffer amplifiers; not allowing direct current (DC) to flow in switches utilized in the multiplexer; and allowing all transients to settle prior to reading out signals from the analog array elements. In a specific embodiment of the invention, the offset compensation is effected for signals being read out from each element of the analog array by sampling and storing a first value representative of a âregularâ output from the multiplexer that is associated with a particular array element and its associated buffer amplifier, sampling and storing a second value representative of a reference output, i. e.

Array Readout System

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US Patent:
6677995, Jan 13, 2004
Filed:
Feb 4, 1999
Appl. No.:
09/244363
Inventors:
Andrew John Blanksby - Neptune NJ
Marc J. Loinaz - New York NY
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04N 314
US Classification:
348301, 348308, 348241, 348294
Abstract:
Problems with source followers employed in active arrays are alleviated by employing a differential amplifier for each element of the active array. However, instead of including an entire differential amplifier within each element, part of the differential amplifier structure is shared among each sensor element connected to a particular column. For example, the differential amplifier may be a differential pair operational transconductance amplifier (OTA) which is connected using a feedback configuration. However, instead of including an OTA within each sensor element of the array, part of the OTA structure is shared among each sensor element connected to a particular column. Although gains greater than one are achievable by employing the differential amplifier with a feedback network, to avoid introducing fixed pattern noise, substantially unity gain is often preferred. Furthermore, the shared differential amplifier model of array reading may be employed for any active array readout application, e. g. , including arrays that are not in themselves per se sensor arrays, where the necessary structure to form the shared differential amplifier is included within the elements of the array.

Activ Shunt-Peaked Logic Gates

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US Patent:
6788103, Sep 7, 2004
Filed:
Aug 6, 2002
Appl. No.:
10/213484
Inventors:
Arnold R. Feldman - San Francisco CA
Marc J. Loinaz - Palo Alto CA
Assignee:
Aeluros, Inc. - Mountain View CA
International Classification:
H03K 1716
US Classification:
326 34, 326 83, 326121
Abstract:
A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic.

Methods And Apparatus For Improving Large Signal Performance For Active Shunt-Peaked Circuits

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US Patent:
7009425, Mar 7, 2006
Filed:
Feb 13, 2004
Appl. No.:
10/778635
Inventors:
Marc J Loinaz - Palo Alto CA, US
Arnold R. Feldman - San Francisco CA, US
Assignee:
Aeluros, Inc. - Mountain View CA
International Classification:
H03K 17/16
US Classification:
326 83, 326121
Abstract:
A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic. Techniques for improving large signal performance for active shunt-peaked circuits are also disclosed.

Methods And Apparatus For Generating Multiple Clocks Using Feedback Interpolation

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US Patent:
7323916, Jan 29, 2008
Filed:
Dec 29, 2005
Appl. No.:
11/321412
Inventors:
Stefanos Sidiropoulos - Palo Alto CA, US
Marc Loinaz - Palo Alto CA, US
R. Shekhar Narayanaswami - Palo Alto CA, US
Nikhil Acharya - Mountain View CA, US
Dean Liu - Sunnyvale CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
H03L 7/06
US Classification:
327156, 157147
Abstract:
A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Methods And Apparatus For Frequency Synthesis With Feedback Interpolation

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US Patent:
7432750, Oct 7, 2008
Filed:
Dec 7, 2005
Appl. No.:
11/296786
Inventors:
Stefanos Sidiropoulos - Palo Alto CA, US
Marc Loinaz - Palo Alto CA, US
R. Shekhar Narayanaswami - Palo Alto CA, US
Nikhil Acharya - Mountain View CA, US
Dean Liu - Sunnyvale CA, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
H03B 21/00
H03L 7/06
US Classification:
327156, 327157, 327105
Abstract:
A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.
Marc J Loinaz from Los Altos Hills, CA, age ~57 Get Report