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Manoj B Roge

from San Ramon, CA
Age ~56
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Also known as:
Manoj Te Roge, Mamoj Roge, Manoj Rogue
Phone and address:
7536 Balmoral Way, San Ramon, CA 94582
Related to:
Kalpana M Roge, 52
Connected to:
Eileen M Roge, 81Steve P Roge, 53Abel G Rogel, 78Arlene B Rogel, 89Benjamin Rogel, 87Carolina C Rogel, 63Chris Rogel, 35Diane F Rogel, 63Dorothy A Rogel, 90Fausto Rogel, 39

Manoj Roge Phones & Addresses

  • 7536 Balmoral Way, San Ramon, CA 94582
  • 5530 Bryce Valley Ct, Cumming, GA 30040 (770) 406-8714
  • Fremont, CA
  • Fort Worth, TX
  • Suwanee, GA
  • San Jose, CA
  • Santa Clara, CA
  • Fairfield, CA
  • Newark, CA
  • Alameda, CA

Work

Company: Open compute project foundation Aug 2016 to Oct 2017 Position: Ocp co-lead

Education

Degree: Master of Business Administration, Masters School / High School: Santa Clara University 2000 to 2003 Specialities: Marketing, Finance

Skills

Semiconductors • Fpga • Product Marketing • Ic • Asic • Soc • Semiconductor Industry • Product Development • Embedded Systems • Product Management • Wireless • Strategy • Processors • Go To Market Strategy • Technical Marketing • Start Ups • Strategic Partnerships • Cross Functional Team Leadership • Management • Dram • Analog • Hardware Architecture • Program Management • Cloud Computing • Engineering Management • Arm • Data Center • Application Specific Integrated Circuits • Partnerships

Languages

English • Hindi • Marathi • Gujarati

Interests

Ciencia Y Tecnología

Industries

Semiconductors

Resumes

Resumes

Manoj Roge Photo 1

Vp, Strategic Planning And Business Development

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Location:
7536 Balmoral Way, San Ramon, CA 94582
Industry:
Semiconductors
Work:
Open Compute Project Foundation Aug 2016 - Oct 2017
Ocp Co-Lead
Achronix Semiconductor Corporation Aug 2016 - Oct 2017
Vp, Strategic Planning and Business Development
Xilinx Dec 1, 2016 - Jul 2017
Director, Data Center Strategy and Marketing
Xilinx Apr 2016 - Dec 2016
Business Lead, Data Center
Xilinx Jul 2014 - Mar 2016
Director, Data Center and Wired Communications Solutions Planning and Marketing
Education:
Santa Clara University 2000 - 2003
Master of Business Administration, Masters, Marketing, Finance The University of Texas at Arlington 1991 - 1994
Masters, Master of Science In Electrical Engineering, Vlsi Design University of Mumbai 1986 - 1990
Bachelor of Engineering, Bachelors, Electronics Engineering, Electronics
Skills:
Semiconductors
Fpga
Product Marketing
Ic
Asic
Soc
Semiconductor Industry
Product Development
Embedded Systems
Product Management
Wireless
Strategy
Processors
Go To Market Strategy
Technical Marketing
Start Ups
Strategic Partnerships
Cross Functional Team Leadership
Management
Dram
Analog
Hardware Architecture
Program Management
Cloud Computing
Engineering Management
Arm
Data Center
Application Specific Integrated Circuits
Partnerships
Interests:
Ciencia Y Tecnología
Languages:
English
Hindi
Marathi
Gujarati

Business Records

Name / Title
Company / Classification
Phones & Addresses
Manoj B. Roge
President
Yash Solutions Inc
1233 Hazlett Ct, San Jose, CA 95131

Publications

Us Patents

Content Addressable Memory Cell

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US Patent:
6480406, Nov 12, 2002
Filed:
Aug 22, 2001
Appl. No.:
09/934813
Inventors:
Bo Jin - Campbell CA
Manoj Roge - San Jose CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 1500
US Classification:
365 49, 365154
Abstract:
Architecture, circuitry, and methods are provided for producing a content addressable memory (CAM). The CAM includes one or more CAM cells arranged in an array. Each CAM cell is symmetrical about its x- and y-axis to form rows and columns of the array. Additionally, each CAM cell can use either SRAM or DRAM storage cells implemented in either a binary or ternary arrangement. If the CAM cell is a ternary SRAM design, then the cell size is no more than 4 microns by 1-Â microns, assuming a 0. 15 micron critical dimension. Critical dimension is noted as the smallest resolvable size for the particular process being employed. The CAM cell utilizes a selection circuitry that will disable the compare circuit during times when a compare operation is not being performed. This will ensure the compare circuit will not consume power during, for example, a read or write operation. Each CAM cell uses no more than eight conductors per cell, wherein the conductors are of minimum width and pitch arranged co-planar on a single metal layer.

Bit Encoded Ternary Content Addressable Memory Cell

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US Patent:
6721202, Apr 13, 2004
Filed:
Dec 21, 2001
Appl. No.:
10/027553
Inventors:
Manoj B. Roge - San Jose CA
Ajay Srikrishna - Fremont CA
Assignee:
Cypress Semiconductor Corp. - San Jose CA
International Classification:
G11C 1156
US Classification:
365168, 365 49, 36518507, 36518902, 36518907, 365226
Abstract:
Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell, the TCAM cell employs no more than 16 transistors. Additional savings in size is achieved by using a single common conductor (or dual common conductors in a differential arrangement) to suffice as both the bit line and compare line. The common bit line and compare line connects to not only the X memory cell, but also the Y memory cell and the compare circuit of the TCAM cell. The compare circuit can either be activated or deactivated. During a compare operation, the compare circuit is selectively activated by placing a ground supply upon a match line enable conductor. The ground supply is imputed upon the match line whenever a mismatch occurs to designate that mismatch.

Memory Device Providing Asynchronous And Synchronous Data Transfer

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US Patent:
6791898, Sep 14, 2004
Filed:
Oct 11, 2002
Appl. No.:
10/269391
Inventors:
Rajesh Manapat - San Jose CA
Manoj Roge - San Jose CA
Kannan Srinivasagam - Sunnyvale CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 800
US Classification:
365233, 3652335, 36523001
Abstract:
Embodiments of the present invention provide a memory device having multiple modes of data transfer. In one embodiment, async/sync logic and a configuration register provide for asynchronous and synchronous data transfer. The async/sync logic utilizes the configuration register and various control signals to determine whether a data transfer operation should be asynchronous or synchronous. The async/sync logic also utilizes the configuration register and various control signals to determine other functionalities of the particular data transfer mode. Functionalities may include normal and page mode, page length, bust read, linear or interleaved burst, burst wrap, burst suspend, data hold length, first access latency, transition between synchronous and asynchronous mode, and the like.

Pvt Compensated Auto-Calibration Scheme For Ddr3

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US Patent:
7590008, Sep 15, 2009
Filed:
Nov 6, 2007
Appl. No.:
11/936036
Inventors:
Manoj B. Roge - San Jose CA, US
Andrew Bellis - Guildford, GB
Philip Clarke - Leatherhead, GB
Joseph Huang - Morgan Hill CA, US
Michael H. M. Chu - Fremont CA, US
Yan Chong - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/00
US Classification:
365189011, 36518915, 36518916, 365193, 365194
Abstract:
Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Read-Leveling Implementations For Ddr3 Applications On An Fpga

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US Patent:
7593273, Sep 22, 2009
Filed:
Nov 5, 2007
Appl. No.:
11/935310
Inventors:
Michael H. M. Chu - Fremont CA, US
Joseph Huang - Morgan Hill CA, US
Chiakang Sung - Milpitas CA, US
Yan Chong - San Jose CA, US
Andrew Bellis - Guildford, GB
Philip Clarke - Leatherhead, GB
Manoj B. Roge - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/10
US Classification:
365194, 365193
Abstract:
Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Memory Device And Method For Fast Cross Row Data Access

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US Patent:
7660167, Feb 9, 2010
Filed:
Mar 28, 2006
Appl. No.:
11/391535
Inventors:
Manoj Roge - San Jose CA, US
Rajesh Manapat - Santa Clara CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G11C 7/10
US Classification:
36518905, 36523006, 36523008
Abstract:
A memory device can provide burst access to row boundary crossing addresses without introducing inter-burst latency. Address locations for a first row of the burst can be accessed at speed, while a prefetch latch can be accessed in lieu of a next row.

Pvt Compensated Auto-Calibration Scheme For Ddr3

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US Patent:
7983094, Jul 19, 2011
Filed:
Aug 11, 2009
Appl. No.:
12/539594
Inventors:
Manoj B. Roge - San Jose CA, US
Andrew Bellis - Guildford, GB
Philip Clarke - Leatherhead, GB
Joseph Huang - Morgan Hill CA, US
Michael H. M. Chu - Fremont CA, US
Yan Chong - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/00
G11C 8/00
US Classification:
365189011, 365193, 365194, 3652331, 36523313
Abstract:
Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

Read-Leveling Implementations For Ddr3 Applications On An Fpga

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US Patent:
7990786, Aug 2, 2011
Filed:
Aug 11, 2009
Appl. No.:
12/539582
Inventors:
Michael H. M. Chu - Fremont CA, US
Joseph Huang - Morgan Hill CA, US
Chiakang Sung - Milpitas CA, US
Yan Chong - San Jose CA, US
Andrew Bellis - Guildford, GB
Philip Clarke - Leatherhead, GB
Manoj B. Roge - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/10
US Classification:
365194, 365193
Abstract:
Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
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Manoj B Roge from San Ramon, CA, age ~56 Get Report