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Lyndon C Lim

from San Jose, CA
Age ~60
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Also known as:
Lyndon Charles Lim, Lyndon Living Lim, Lyndon Te Lim, Lindon C Yew
Phone and address:
1199 Valley Quail Cir, San Jose, CA 95120
(408) 268-0668
Related to:
Caroline K Siy, 59Annabelle F Lim, 46Pearl C Yew, 63Simon Lim, 64Alise Lim, 32
Connected to:
Aesop L Lim, 61Aina H Lim, 47Alan R Lim, 58Albert J Lim, 40Alexis Lim, 43Alexson Lim, 36Alfian Lim, 50Allyn T Lim, 35Alma R Lim, 67Alvyn Y Lim, 35

Lyndon Lim Phones & Addresses

  • 1199 Valley Quail Cir, San Jose, CA 95120 (408) 268-0668
  • 1076 Queensbridge Ct, San Jose, CA 95120 (408) 997-7717
  • 864 Mulcaster Ct, San Jose, CA 95136 (408) 997-7717
  • Campbell, CA
  • Sanger, CA
  • Santa Clara, CA

Work

Company: Intel corporation Jan 2016 to May 2017 Position: Cad engineer

Skills

Eda • Ic • Semiconductors • Mixed Signal • Physical Design • Integrated Circuit Design • Asic • Python • Circuit Design • Soc • Simulations • Analog • Physical Verification • Cad • Cadence Virtuoso • Cadence Skill • Customer Engagement • Lvs • Linux System Administration • Verilog • Arm • Pdk • Perl • Cmos • Automation • Tcl • Vlsi • Customer Support • Silicon • Drc • Place and Route • Scripting

Industries

Semiconductors

Resumes

Resumes

Lyndon Lim Photo 1

Full Chip Physical Integration Engineer

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Location:
San Jose, CA
Industry:
Semiconductors
Work:
Intel Corporation Jan 2016 - May 2017
Cad Engineer
Intel Corporation Jan 2016 - May 2017
Full Chip Physical Integration Engineer
Altera Sep 2013 - Dec 2015
Principal Cad Engineer
Synopsys Aug 2012 - Sep 2013
Senior Staff R and D Engineer
Ciranova Aug 2005 - Aug 2012
Principal Cad Engineer
Skills:
Eda
Ic
Semiconductors
Mixed Signal
Physical Design
Integrated Circuit Design
Asic
Python
Circuit Design
Soc
Simulations
Analog
Physical Verification
Cad
Cadence Virtuoso
Cadence Skill
Customer Engagement
Lvs
Linux System Administration
Verilog
Arm
Pdk
Perl
Cmos
Automation
Tcl
Vlsi
Customer Support
Silicon
Drc
Place and Route
Scripting

Publications

Us Patents

Cell Architecture With Local Interconnect And Method For Making Same

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US Patent:
6594813, Jul 15, 2003
Filed:
Oct 31, 2000
Appl. No.:
09/703975
Inventors:
Dhrumil Gandhi - Cupertino CA
Lyndon C. Lim - San Jose CA
Assignee:
Artisan Components, Inc. - Sunnyvale CA
International Classification:
G06F 1750
US Classification:
716 17
Abstract:
Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit. In a preferred embodiment, the local interconnect metallization lines are configured to be fabricated from a higher resistivity metal having a resistivity that is greater than aluminum containing metals.

System And Method For Proxied Evaluation Of Pcells

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US Patent:
7698662, Apr 13, 2010
Filed:
Jul 21, 2006
Appl. No.:
11/490678
Inventors:
Felix Sun-Tsyr Wu - San Jose CA, US
Edwin Simon Petrus - Piedmont CA, US
Lyndon Charles Lim - San Jose CA, US
Assignee:
Ciranova, Inc. - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 18
Abstract:
Systems and methods of laying out integrated circuits are disclosed. During the layout stage of an integrated circuit device, a fixed, physical geometry is created of the parameterized cells (PCells) included in the integrated circuit schematic. The systems include a proxy engine configured to save to cache the geometries created during the layout stage such that the geometries need not be recomputed when the design is opened after a save to disk operation, during which geometries may otherwise be destroyed. The proxy engine may further be configured to delegate requests for the creation of geometries to other components of the integrated circuit design system. In addition, the proxy engine may be configured to perform customized evaluations of PCells, other than or in addition to caching and delegation.

Cell Architecture With Local Interconnect And Method For Making Same

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US Patent:
20010045571, Nov 29, 2001
Filed:
Sep 23, 1998
Appl. No.:
09/159264
Inventors:
DHRUMIL GANDHI - CUPERTINO CA, US
LYNDON C. LIM - SAN JOSE CA, US
International Classification:
H01L027/10
US Classification:
257/202000
Abstract:
Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit. In a preferred embodiment, the local interconnect metallization lines are configured to be fabricated from a higher resistivity metal having a resistivity that is greater than aluminum containing metals.

Concurrent Placement And Routing Using Hierarchical Constraints

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US Patent:
20130219353, Aug 22, 2013
Filed:
Feb 17, 2012
Appl. No.:
13/399803
Inventors:
Lindor E. Henrickson - San Francisco CA, US
Lyndon C. Lim - San Jose CA, US
International Classification:
G06F 17/50
US Classification:
716122
Abstract:
An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints.
Control profile
Lyndon C Lim from San Jose, CA, age ~60 Get Report