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Lucas M Jenison

from Beaverton, OR
Age ~46
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Also known as:
Lucas Martin Jenison, Lucas Katie Jenison, Luke M Jenison, Martin Jenison Lucas, Jenison M Lucas
Phone and address:
7995 SW Carol Glen Pl, Beaverton, OR 97007
(503) 522-4530
Related to:
Virginia C Jenison, 93Jennie M Gonzales, 45Katie Jenison, 47Joanne M Sexton, 73Dixie L Bart, 77Katie J Jenison, 40Corey L Jenison, 43L JenisonInu Jenison, 99Julie L Jenison, 62Harold C JenisonKerri L JenisonGlenn E Sexton, 72Diane R Sexton, 42Thomas M Jenison, 70Ken E Bart, 77Elizabeth A Jenison, 68
Connected to:
Cheryl A Jenison, 77David E Jenison, 41Melissa A Jenista, 34Drew T Jenk, 45Paul R Jenke, 99Dennis M Jenkerson, 36William I Jenkerson, 77Abbie D Jenkin, 55Bailey J Jenkin, 30Belinda Jenkin, 53

Lucas Jenison Phones & Addresses

  • 7995 SW Carol Glen Pl, Beaverton, OR 97007 (503) 522-4530
  • 2824 Moda Way, Hillsboro, OR 97124 (503) 629-7240
  • Aloha, OR
  • 7321 Astronaut Ave, Jenison, MI 49428 (616) 457-5024
  • Portland, OR

Work

Company: Intel corporation Position: Component design engineer

Education

School / High School: University of Michigan 1996 to 2000

Industries

Computer Hardware

Resumes

Resumes

Lucas Jenison Photo 1

Component Design Engineer

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Location:
15320 southwest Jasper Ln, Beaverton, OR 97007
Industry:
Computer Hardware
Work:
Intel Corporation
Component Design Engineer
Education:
University of Michigan 1996 - 2000

Publications

Us Patents

Data Reception Management Apparatus, Systems, And Methods

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US Patent:
8473579, Jun 25, 2013
Filed:
May 10, 2012
Appl. No.:
13/468151
Inventors:
Patrick L. Connor - Portland OR, US
Linden Minnick - Hillsboro OR, US
Lucas M. Jenison - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15/16
G06F 15/173
US Classification:
709217, 709224, 709226
Abstract:
Apparatus, systems, and methods to manage networks may operate to receive a packet into an element of an array contained in a memory while a low resource state exists, and to truncate the array at the element responsive to at least one of an indication that the array is full, or an indication that no more packets are available to be received after receiving at least the packet. The receiving and the truncating may be executed by a processor. Additional apparatus, systems, and methods are disclosed.

Reducing Memory Copies By A Network Controller

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US Patent:
20020138655, Sep 26, 2002
Filed:
Mar 21, 2001
Appl. No.:
09/814362
Inventors:
Lucas Jenison - Hillsboro OR, US
Linden Minnick - Hillsboro OR, US
International Classification:
G06F015/16
G06F003/00
US Classification:
709/250000, 710/052000
Abstract:
The number of memory copies in a network may be reduced by monitoring the state of the controller resources. If the controller resources run low while processing an array of data packets, the current data packet is marked and all subsequent data packets are flagged. When the array is fully processed, the controller resources are checked again. If the resources are still low, the flagged data packets are copied to buffers. However, if the controller resources are no longer low, the network controller removes all the flags and the data packets may be copied directly into the host memory at a later time.

Driver Having Multiple Deferred Procedure Calls For Interrupt Processing And Method For Interrupt Processing

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US Patent:
20020144004, Oct 3, 2002
Filed:
Mar 29, 2001
Appl. No.:
09/823155
Inventors:
Daniel Gaur - Beaverton OR, US
Patrick Connor - Portland OR, US
Lucas Jenison - Hillsboro OR, US
Patrick Luhmann - Hillsboro OR, US
Linden Minnick - Hillsboro OR, US
International Classification:
G06F009/46
G06F015/163
G06F009/54
G06F009/00
US Classification:
709/310000
Abstract:
A driver having an interrupt service routine including an interrupt handler and at least two deferred procedure calls. Each of the at least two deferred procedure calls is associated with a particular interrupt event or type of interrupt event. If multiple interrupt events occur, the interrupt events may be concurrently processed on separate deferred procedure calls, resulting in a substantially reduced interrupt handling latency.

Data Reception Management Apparatus, Systems, And Methods

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US Patent:
20030236911, Dec 25, 2003
Filed:
Jun 25, 2002
Appl. No.:
10/183185
Inventors:
Patrick Connor - Portland OR, US
Linden Minnick - Hillsboro OR, US
Lucas Jenison - Hillsboro OR, US
Assignee:
Intel Corporation
International Classification:
G06F015/16
US Classification:
709/234000, 709/250000
Abstract:
Computer network apparatus may include a packet-receiving module to receive a packet into an element of a storage array while a low resource state exists, an array truncation module to truncate the array at the element when the array is full or when no more packets are available to be received, and an array indication module to indicate the array after the array truncation module truncates the array. In one embodiment, a system may include a receiving node containing the apparatus. A method may include receiving a packet into an element of an array while a low resource state exists, truncating the array at the element after the array is full or no more packets are available to be received, and indicating the array.
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Lucas M Jenison from Beaverton, OR, age ~46 Get Report