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Loren C Krott

from Kennebunk, ME
Age ~58

Loren Krott Phones & Addresses

  • 5 Larrabee Way, Kennebunk, ME 04043 (207) 318-3473
  • 74 Spiller Rd, Gorham, ME 04038 (207) 839-3218
  • 80 Spiller Rd, Gorham, ME 04038 (207) 839-3218
  • Santa Clara, CA
  • Dolgeville, NY
  • Rochester, NY

Work

Company: Mmqci-maine molecular quality controls Mar 2020 Position: Manager of manufacturing operations

Education

Degree: Master of Business Administration, Masters School / High School: San Jose State University 1993 to 1995 Specialities: Business

Industries

Semiconductors

Resumes

Resumes

Loren Krott Photo 1

Manager Of Manufacturing Operations

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Location:
5 Larrabee Way, Kennebunk, ME 04043
Industry:
Semiconductors
Work:
Mmqci-Maine Molecular Quality Controls
Manager of Manufacturing Operations

Rochester Electronics
Vice President Strategy and Business Development, Manufacturing

Rochester Electronics 2008 - Dec 2009
Product Engineering Manager

Rochester Electronics 2008 - Dec 2009
Director of Technology

National Semiconductor Jun 2007 - Feb 2008
Yield Improvement Project Manager
Education:
San Jose State University 1993 - 1995
Master of Business Administration, Masters, Business
Rochester Institute of Technology 1984 - 1991
Rochester Institute of Technology
Bachelors, Bachelor of Science

Publications

Us Patents

System And Method For Using Areas Near Photo Global Alignment Marks Or Unpatterned Areas Of A Semiconductor Wafer To Create Structures For Sims Or E-Beam Or Xrd Testing

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US Patent:
7038222, May 2, 2006
Filed:
Jun 16, 2004
Appl. No.:
10/869681
Inventors:
Thanas Budri - Portland ME, US
Aaron Michael Smith - Harpswell ME, US
Neil Suresh Patel - Portland ME, US
Loren Charles Krott - Gorham ME, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21/66
G01R 31/26
US Classification:
2504922, 2504923, 250306, 250307, 250309, 250310, 700121, 257E21001
Abstract:
A system and method is described for using areas in or near photo global alignment marks or in or near unpatterned areas of a semiconductor wafer to create structures for secondary ion mass spectroscopy (SIMS) testing or electron beam (E-Beam) testing or X-ray diffraction (XRD) testing of the semiconductor wafer. The present invention makes it possible to obtain wafer level information about the front-end processing of the semiconductor wafers. The SIMS/E-Beam/XRD testing measures characteristics such as the dopant content, thickness variations, and defect density of the wafers. The present invention eliminates the need to build individual test structures within product dies and eliminates the need to build scribe line structures near the product dies.
Loren C Krott from Kennebunk, ME, age ~58 Get Report