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Lohit R Yerva

from Mountain View, CA
Age ~35
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Also known as:
Lohit W Yerva
Related to:
Matt J Strozeski, 49Samantha R Strodel, 35Yeruva Suryanarayana, 63Sneha Reddy, 33Surya R Yerva, 63Anuradha Y Reddy, 61
Connected to:
Daniel C Yerves, 35Gerald A Yerxa, 97Mitchell S Yerxa, 36Jan A Yerzik, 64Arman Yerzinkyan, 51Talin Yesaie, 44Alia A Yesalavage, 49Miguel R Yesan, 85Steven M Yesavage, 71Anna Yesayan, 47

Lohit Yerva Phones & Addresses

  • Mountain View, CA
  • Sunnyvale, CA
  • Hillsboro, OR
  • Ann Arbor, MI
  • Troy, MI
  • San Diego, CA

Publications

Us Patents

Logic Die In A Multi-Chip Package Having A Configurable Physical Interface To On-Package Memory

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US Patent:
20210225827, Jul 22, 2021
Filed:
Mar 26, 2021
Appl. No.:
17/213791
Inventors:
- Santa Clara CA, US
Lohit YERVA - Mountain View CA, US
Mohammad RASHID - San Jose CA, US
Kuljit S. BAINS - Olympia WA, US
International Classification:
H01L 25/18
H01L 25/065
H01L 23/538
Abstract:
A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.

Technology To Provide Accurate Training And Per-Bit Deskew Capability For High Bandwidth Memory Input/Output Links

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US Patent:
20200393997, Dec 17, 2020
Filed:
Sep 1, 2020
Appl. No.:
17/009241
Inventors:
- Santa Clara CA, US
Kuljit Bains - Olympia WA, US
Lohit Yerva - Mountain View CA, US
International Classification:
G06F 3/06
G06F 13/16
G06F 11/10
G06N 20/00
Abstract:
Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.

Device, System And Method To Generate Link Training Signals

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US Patent:
20200042209, Feb 6, 2020
Filed:
Apr 22, 2019
Appl. No.:
16/390551
Inventors:
- Santa Clara CA, US
Moshe Jacob Finkelstein - Kfar Saba, IL
Ramesh Subashchandrabose - Bangalore, IN
Lohit R. Yerva - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/06
G06N 20/00
Abstract:
Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.
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Lohit R Yerva from Mountain View, CA, age ~35 Get Report