Inventors:
Lawrence Pileggi - Pittsburgh PA
Christopher Dunn - Sunnyvale CA
Satyamurthy Pullela - Cupertino CA
Majid Sarrafzadeh - Wilmette IL
Tong Gao - Mountain View CA
Salil Raje - Santa Clara CA
Assignee:
Monterey Design Systems, Inc. - Sunnyvale CA
International Classification:
G06F 1750
Abstract:
Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i. e. , prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.
