Lance A Marten

6590949, Jul 8, 2003

Feb 11, 1999

09/247971

Lance Alan Marten - Gilbert AZ
William H. Gulliver - Gilbert AZ
Bradley Michael Wemhaner - Chandler AZ

Motorola, Inc. - Schaumburg IL

H03D 324

375376, 375374, 327147, 327148, 327156, 327157

A Phase Locked Loop system ( ) provides the signals UP and DOWN for a charge pump ( ). The charge pump ( ) supplies a biasing signal to a voltage controlled oscillator ( ). The phase and frequency relationship between a feedback signal from the voltage controlled oscillator ( ) and a clock signal are used by a compensating phase-frequency detector ( ) to generate the signals UP and DOWN. The pulse width of the signal DOWN is limited when a transition of the clock signal is missed. An error detector ( ) provides a signal BADCLK after detecting that multiple transitions of the clock signal have been missed. The signal BADCLK generates the signal UP having a pulse width that compensates for the last signal DOWN and keeps the biasing signal to the voltage controlled oscillator ( ) relatively constant when the clock signal fails.

62224204, Apr 24, 2001

Sep 13, 2000

9/660747

William H. Gulliver - Gilbert AZ
Lance A. Marten - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H03L 706
H03L 710
H03L 7089

331 14

A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

61508896, Nov 21, 2000

Aug 3, 1998

9/128025

William H. Gulliver - Gilbert AZ
Lance A. Marten - Gilbert AZ

Motorola, Inc. - Schaumburg IL

H03L 706
H03L 710
H03L 7089

331 14

A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.