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Lal C Sood

from Austin, TX
Age ~80
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Also known as:
Lal Lily Sood, Sood Lal, Chand Sood Lal
Phone and address:
4204 Dunning Ln, Austin, TX 78746
(512) 327-1124
Related to:
Chetan Sood, 43Rekha Sood VishalSharad SoodLily Sood, 74Rajesh Sood, 38Raj Sood, 79Wtp Sood
Connected to:
Angela N Sood, 43Annu Sood, 40Anshul Sood, 38Apoorva Sood, 36Arjun Sood, 35Arpan Sood, 46Ashima Sood, 35Avi N Sood, 78Bhuvnesh Sood, 61

Lal Sood Phones & Addresses

  • 4204 Dunning Ln, Austin, TX 78746 (512) 327-1124 (512) 330-0297 (512) 531-9361
  • 4204 Dunning Ln, Austin, TX 78746 (512) 531-9361

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Resumes

Resumes

Lal Sood Photo 1

Owner-Founder

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Medical Software Solutions/World Technology Partners
Owner-Founder
Ofdm Wireless Jan 2002 - Dec 2002
Vice President of Technology
Amd/Silicon Lab Jan 2001 - Dec 2001
Consultant
Vignette Jun 2000 - Dec 2000
Vice President of Operations
Motorola Semiconductor/Freescale Jan 1998 - May 2000
Director of Engineering and Operations
Education:
South Dakota School of Mines and Technology
Masters, Master of Science In Electrical Engineering, Electrical Engineering Punjab Engineering College
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Custom Circuit Design
Vlsi Design
Sram/Flash Design
Healthcare It
Medical Software
Project Management
Operations
Managing Multiple Locations
Collaborative Project Management
International Project Management
Lal Sood Photo 2

Lal Sood

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Lal C Sood
President, Director
WORLD TECHNOLOGY PARTNERS INC
4204 Dunning Ln, Austin, TX 78746

Publications

Us Patents

Circuit For Generating Test Equalization Pulse

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US Patent:
45491011, Oct 22, 1985
Filed:
Dec 1, 1983
Appl. No.:
6/556761
Inventors:
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 504
H03K 17693
US Classification:
307443
Abstract:
A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address transition signals are received by a multi-input logic circuit which causes the equalization pulse to be present at least as long as a signal is present at one of the inputs. A test pad on the integrated circuit receives an externally generated test signal of variable duration. The test signal is coupled to an input of the logic circuit to generate the equalization pulse for the duration of the test signal.

Output Circuit In Which Induced Switching Noise Is Reduced By Presetting Pairs Of Output Lines To Opposite Logic States

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US Patent:
47243406, Feb 9, 1988
Filed:
Nov 21, 1986
Appl. No.:
6/933424
Inventors:
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 1716
H03K 1720
US Classification:
307443
Abstract:
An integrated circuit has a plurality of outputs which switch to a valid condition at the same time. Because integrated circuits have leads for power supply terminals, there is inductance on these leads. When an output switches logic states, there is a change in current flow so that there is a voltage drop across the inductive lead which is used for power supply coupling. This voltage drop, expressed Ldi/dt, is proportional to the number of outputs which are switched. The worst case for the positive power supply terminal Ldi/dt is when all of the outputs switch from a logic low to a logic high. This worst case is reduced in half by predisposing half of the outputs to one logic state and the other half to the other logic state. This also reduces the worst case for the negative power supply terminal, frequently ground, in half which is the case when all of the outputs switch from a logic high to a logic low.

Buffer Circuit

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US Patent:
44674554, Aug 21, 1984
Filed:
Nov 1, 1982
Appl. No.:
6/438085
Inventors:
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 700
US Classification:
365189
Abstract:
An input buffer circuit for a memory uses two transistors interposed between a push-pull pair of transistors to control the enabling of the buffer in response to a chip write signal generated from a logical combination of chip select and write enable signals. A plurality of inverters which provide complementary signals to the push-pull transistors are disabled and prevented from using current by an interrupt transistor until the interrupt transistor receives the chip write signal.

High Speed Input Buffer Having Substrate Biasing To Increase The Transistor Threshold Voltage For Level Shifting

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US Patent:
46124616, Sep 16, 1986
Filed:
Feb 9, 1984
Appl. No.:
6/578718
Inventors:
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H03K 1730
H03K 19096
US Classification:
307475
Abstract:
An input buffer which can be used as a TTL to CMOS input buffer in a CMOS integrated circuit has a CMOS input inverter for receiving an external input signal. The typical threshold voltage of the P and N channel transistors is relatively low for high speed operation. At least one of the P and N channel transistors of the input inverter has the magnitude of its threshold voltage increased by applying appropriate back bias voltage in the well in which it resides.

High Speed Equalization In A Memory

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US Patent:
47121971, Dec 8, 1987
Filed:
Jan 28, 1986
Appl. No.:
6/823446
Inventors:
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 800
US Classification:
365230
Abstract:
A memory is comprised of memory cells located at intersections of word lines and bit line pairs. The memory has a read mode in which data is read from a bit line pair selected by a column address. The data to be read is provided to bit line pairs by the memory cells which are coupled to a word line which has been selected to be enabled by a row address. In the write mode, data is written to a memory cell which is coupled to an enabled word line and which is coupled to a bit line pair into which data has been selected to be written. The pairs of bit lines are equalized in voltage in response to not only an address transition but also in response to a transition from the write mode to the read mode.

Semiconductor Memory With Divided Word Lines And Shared Sense Amplifiers

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US Patent:
47978589, Jan 10, 1989
Filed:
Mar 30, 1987
Appl. No.:
7/031305
Inventors:
Karl L. Wang - Austin TX
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 700
US Classification:
365230
Abstract:
A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this unique organization of the memory array to provide for sense amplifier sharing. This feature allows fewer, and larger sense amplifiers for better performance.

Bit Line Precharge In A Bimos Ram

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US Patent:
48993174, Feb 6, 1990
Filed:
Feb 1, 1988
Appl. No.:
7/151044
Inventors:
George P. Hoekstra - Fair Oaks CA
Lal C. Sood - Austin TX
Samuel E. Alexander - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 1140
US Classification:
365203
Abstract:
In a static random access memory in which the array is comprised of MOS transistors and at least some of the peripheral circuits are comprised of bipolar transistors, the bit lines and data lines are precharged to a base to emitter voltage drop (i. e. one Vbe) below the positive power supply voltage. This increases cell stability. Additionally, Vbe varies comparatively little over process. Additionally, precharging the bit lines and data lines to a Vbe below the positive power supply voltage allows for the use of a high speed bipolar differential amplifier in its optimum operating range as the first stage sense amplifier.

Data Processor Having Instruction Varied Set Associative Cache Boundary Accessing

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US Patent:
52108422, May 11, 1993
Filed:
Feb 4, 1991
Appl. No.:
7/650108
Inventors:
Lal C. Sood - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1208
G06F 1204
G11C 700
US Classification:
395425
Abstract:
A data processor having an instruction varied set associative cache boundary access capability provides reduced power consumption and maintains data processor performance. Queued data processor operation codes are partially decoded within an intermediate stage of an instruction pipe of the data processor to provide information on pending instructions. The information provided determines if a pending instruction will require either a full or a partial output line of information from the set associative cache. When the provided information from the instruction pipe indicates that an instruction will require a full output line of information to complete execution, the set associative cache provides the full output line of information. Otherwise, the set associative cache provides only a partial output line of information.
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Lal C Sood from Austin, TX, age ~80 Get Report