Lakshmi S Murthy

20230068494, Mar 2, 2023

Aug 24, 2021

17/410657

- Cupertino CA, US
Gregory S. Mathews - Saratoga CA, US
Lakshmi Narasimha Murthy Nukala - Pleasanton CA, US

G06F 3/06

Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

20200301615, Sep 24, 2020

Jun 8, 2020

16/896027

- Cupertino CA, US
Gregory S. Mathews - Saratoga CA, US
Lakshmi Narasimha Murthy Nukala - Pleasanton CA, US
Thejasvi Magudilu Vijayaraj - San Jose CA, US
Kai Lun Hsiung - Fremont CA, US
Yanzhe Liu - Sunnyvale CA, US
Sukalpa Biswas - Fremont CA, US

G06F 3/06

An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

20200081622, Mar 12, 2020

Sep 9, 2019

16/565386

- Cupertino CA, US
Shane J. Keil - San Jose CA, US
Sukalpa Biswas - Fremont CA, US
Lakshmi Narasimha Murthy Nukala - Pleasanton CA, US

G06F 3/06

A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

20200065028, Feb 27, 2020

Aug 24, 2018

16/112624

- Cupertino CA, US
Gregory S. Mathews - Saratoga CA, US
Lakshmi Narasimha Murthy Nukala - Pleasanton CA, US
Thejasvi Magudilu Vijayaraj - San Jose CA, US
Kai Lun Hsiung - Fremont CA, US
Yanzhe Liu - Sunnyvale CA, US
Sukalpa Biswas - Fremont CA, US

G06F 3/06

An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.