Kwang S Kim

6424190, Jul 23, 2002

Sep 13, 2001

09/950572

Kwang Y. Kim - Irvine CA

Broadcom Corporation - Irvine CA

H03L 700

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

6531918, Mar 11, 2003

Nov 10, 1998

09/189642

Richard D. Posner - Woodland Hills CA
Charles R. Gentzler - Thousand Oaks CA
Kwang Kim - Northridge CA
Do B. Shin - Laguna Hills CA

Powerwave Technologies, Inc. - Santa Ana CA

H03F 126

330151, 330149

The invention relates to a low cost feed forward RF power amplifier arrangement for amplifying an RF input signal using a main power amplifier operating as a class A/B amplifier. The method and apparatus modify the input signal to the main amplifier to compensate for the distortion added by the main power amplifier. The circuit provides for injecting a delayed version of the input signal, through a fixed gain-phase circuity, at a point whereby the resulting signal is amplified by the error amplifier of the second loop. A digitally controlled processor iteratively modifies various phase and gain controls to adjust the output of the amplifier. Different gain and phase control lines are iteratively updated at different rates.

6597216, Jul 22, 2003

Jul 19, 2002

10/197843

Kwang Y. Kim - Irvine CA

Broadcom Corporation - Irvine CA

H03L 700

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

6906564, Jun 14, 2005

Jul 21, 2003

10/622708

Kwang Y. Kim - Irvine CA, US

Broadcom Corporation - Irvine CA

H03L007/00

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

6975557, Dec 13, 2005

Apr 27, 2004

10/832262

Lionel J. D'Luna - Irvine CA, US
Mark Chambers - Mission Viejo CA, US
Thomas Hughes - Dana Point CA, US
Kwang Y. Kim - Irvine CA, US
Sathish K. Radhakrishnan - Karnataka, IN

Broadcom Corporation - Irvine CA

G11C008/00

365233, 365193, 365194

A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.

6998885, Feb 14, 2006

Oct 7, 2004

10/959512

Kwang Y. Kim - Irvine CA, US

Broadcom Corporation - Irvine CA

H03L 7/00

327144, 327258, 327309

A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

7079535, Jul 18, 2006

Jul 27, 2001

09/917575

Kwang H. Kim - Irvine CA, US

The Regents of the Universtiy of California - Oakland CA

H04L 12/56

370390, 370242

The sender of a multicast in a computer network attaches an official release time to the message being multicast, asking every receiver to process the message at or after the official release time. A receiver may receive a cancellation notice after receiving the multicast message but before its official release time. The official release time is chosen so that the multicast can succeed or be cancelled by the official release time with the probability at or above a user selected level under reasonably bounded numbers of occurrences of permanent and temporary faults and reasonably bounded durations of temporary faults. This multicast protocol is formulated to suit the environment where it is not worth it for a node to wait for a reply from another node beyond a certain time-period, called the timeout period.

7205826, Apr 17, 2007

May 27, 2004

10/854635

Kwang Young Kim - Irvine CA, US
Josephus A. E. P. van Engelen - Aliso Viejo CA, US

Broadcom Corporation - Irvine CA

G05F 1/10

327538

A power-down biasing circuit including a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first capacitor connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches. Each current mirror has a first PMOS transistor whose drain is connected to a drain of a corresponding one of the plurality of NMOS transistors through a second switch, whose gate is connected to the drain of the corresponding one of the plurality of NMOS transistors and whose source is connected to a supply voltage; a second capacitor connected between the gate of the first PMOS transistor and the supply voltage; and at least two PMOS transistors are connected as a current multiplier to the output switches. A second NMOS transistor may be added in parallel with the current source, with a gate that is driven by the same signal that drives the first switch. A third NMOS transistor may be added in parallel with the current multiplier, with a gate that is driven by an inverse of the signal that drives the first switch.