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Kurt F Baty

from Austin, TX
Age ~71
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Also known as:
Kurt Francis Baty
Phone and address:
5402 Doss Rd, Austin, TX 78734
(512) 266-0238
Related to:
Susan M BatySusan M Baty, 67Michelle Doty, 70Virginia Baty
Connected to:
Alicia Baty, 46Brandon J Baty, 52Burt W Baty, 79Byron L Baty, 62Cheryll A Baty, 68Darren J Baty, 57Donald A Baty, 82Grant D Baty, 44Jack L Baty, 68Jackie L Baty, 81

Kurt Baty Phones & Addresses

  • 5402 Doss Rd, Austin, TX 78734 (512) 266-0238
  • 26 Hill St, Medway, MA 02053 (508) 429-4198

Industries

Computer Hardware

Public records

Vehicle Records

Kurt Baty

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Address:
5402 Doss Rd, Austin, TX 78734
VIN:
1G1RC6E42BU100036
Make:
CHEVROLET
Model:
VOLT
Year:
2011

Resumes

Resumes

Kurt Baty Photo 1

Kurt Baty

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Location:
Austin, TX
Industry:
Computer Hardware

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kurt Baty
President , Director
ALAMO LITERARY ARTS MAINTENANCE ORGANIZATION, INC
2315 Chimney Hl Dr, Arlington, TX 76012
12917 Candlestick Pl, Austin, TX 78727
Kurt Baty
Owner
W S F D B Consulting
Business Consulting Services
5402 Doss Rd, Austin, TX 78734
(512) 266-0238
Kurt Baty
Director
FANDOM ASSOCIATION OF CENTRAL TEXAS
Membership Organization
PO Box 26442, Austin, TX 78755
PO Box 20472, Austin, TX 78755

Publications

Us Patents

Fault Tolerant Digital Data Processor With Improved Bus Protocol

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US Patent:
49396439, Jul 3, 1990
Filed:
Jul 29, 1987
Appl. No.:
7/079223
Inventors:
William L. Long - Pembroke MA
Robert F. Wambach - Attleboro MA
Kurt F. Baty - Medway MA
Joseph M. Lamb - Hopedale MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1300
G06F 1342
US Classification:
364200
Abstract:
A fault-tolerant digital data processor includes a peripheral device controller for communicating with one or more peripheral devices over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing information. Each peripheral device includes a device interface for transferring information signals between the associated peripheral device and the peripheral bus. The peripheral device controller includes a strobe element connected with the first and second input/output buses for transmitting thereon duplicative, synchronous and simultaneous strobe signals. These strobe signals define successive timing intervals for information transfers along the peripheral bus. Information transfers are normally effected by the transmission of duplicate information signals synchronously and simultaneously on the first and second input/output buses. A transfer cycle element includes a scanner cycle element to determine an operational state of at least one of the peripheral devices connected to the peripheral bus; a command cycle element for executing a command cycle for controlling operation of an attached peripheral device; a read cycle element for effecting the transfer of data signals from the peripheral device to the input/output controller; and a write cycle element for transferring data signals from the input/output controller an attached peripheral device.

Digital Data Processor With Fault-Tolerant Peripheral Interface

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US Patent:
49741446, Nov 27, 1990
Filed:
Jun 16, 1989
Appl. No.:
7/368124
Inventors:
William L. Long - Pembroke MA
Robert F. Wambach - Attleboro MA
Kurt F. Baty - Medway MA
Joseph M. Lamb - Hopedale MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1116
G06F 1300
US Classification:
364200
Abstract:
A fault-tolerant digital data processing system comprises a first input-output controller which communicates with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals from the input/output controller to the peripheral device. A device interface is coupled to the first and second input/output buses and to an associated peripheral device for transferring information between the buses and the associated peripheral device. In normal operation, the device interface applies duplicate information signals synchronously and simultaneously to the input/output buses for transfer to the input/output controller. The device interface also receives, in the absence of fault, duplicative information signal synchronously and simultaneously from the first and second input/output buses.

Digital Data Processor With High Reliability

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US Patent:
46548572, Mar 31, 1987
Filed:
Aug 2, 1985
Appl. No.:
6/762039
Inventors:
Joseph E. Samson - Dover MA
Kenneth T. Wolff - Medway MA
Robert Reid - Dunstable MA
Gardner C. Hendrie - Marlboro MA
Daniel M. Falkoff - Natick MA
Ronald E. Dynneson - Brighton MA
Daniel M. Clemson - Weston MA
Kurt F. Baty - Medway MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1120
US Classification:
371 68
Abstract:
A fualt-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Fault Tolerant Digital Data Processor With Improved Input/Output Controller

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US Patent:
49741500, Nov 27, 1990
Filed:
Jun 16, 1989
Appl. No.:
7/368125
Inventors:
William F. Long - Pembroke MA
Robert F. Wambach - Attleboro MA
Kurt F. Baty - Medway MA
Joseph M. Lamb - Hopedale MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1116
G06F 1300
US Classification:
364200
Abstract:
A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.

Computer Peripheral Control Apparatus

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US Patent:
44868260, Dec 4, 1984
Filed:
Oct 1, 1981
Appl. No.:
6/307524
Inventors:
Kenneth T. Wolff - Medway MA
Joseph E. Samson - Dover MA
Kurt F. Baty - Medway MA
Assignee:
Stratus Computer, Inc. - Natick MA
International Classification:
G06F 1516
G06F 1506
US Classification:
364200
Abstract:
A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units. Arbitration circuits of unusual speed and simplicity provide units of the computing module with access to the common bus structure according to the priority of each unit. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure.

Optimized Interconnect Networks

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US Patent:
52437043, Sep 7, 1993
Filed:
May 8, 1992
Appl. No.:
7/884257
Inventors:
Kurt F. Baty - Medway MA
Charles J. Horvath - Boston MA
Richard C. Clemson - Newton MA
Scott J. Bleiweiss - Wrentham MA
Kenneth T. Wolff - Harvard MA
Assignee:
Stratus Computer - Marlboro MA
International Classification:
G06F 1340
US Classification:
395325
Abstract:
A multinodal system is one-way interconnected, two-way interconnected or, more generally, (n)-way interconnected, where (n) is an integer. In a one-way interconnected system, only one connection element couples any two nodes. Or, put another way, only one communication path exists between every node and every other node. A two-way interconnected system, on the other hand, has two connection elements coupling each pair of nodes. Likewise, an (n)-way interconnected system provides (n) independent connection paths between each pair. Such systems are characteristic in that the relationship between the number of independent buses (b), the number of nodes (v), the number of ports (r), and the degree of interconnectedness (n) can be expressed by the equation ##EQU1## Two-way and (n)-way interconnect arrays may be adapted for use in fault-tolerant communications.

Method And Apparatus For Monitoring Peripheral Device Communications

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US Patent:
49319221, Jun 5, 1990
Filed:
Jul 29, 1987
Appl. No.:
7/079218
Inventors:
Kurt F. Baty - Medway MA
Joseph M. Lamb - Hopedale MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1300
G06F 1342
US Classification:
364200
Abstract:
A fault-tolerant digital data processing system comprises at least a first peripheral controller communicating with at least one peripheral device over a peripheral device bus having first and second input/output buses, each carrying data, address, control, and timing signals. The first peripheral controller includes a first device interface element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The first device interface element also receives, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses. A second peripheral controller is coupled to the peripheral device bus for receiving the first and second input signals identically with the first peripheral controller. The second peripheral controller includes a second device interface element for applying at least one of those input signals to the second input/output controller.

Digital Data Processor With Fault Tolerant Peripheral Bus Communications

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US Patent:
49263153, May 15, 1990
Filed:
Jul 29, 1987
Appl. No.:
7/079297
Inventors:
William L. Long - Pembroke MA
Robert F. Wambach - Attleboro MA
Kurt F. Baty - Medway MA
Joseph M. Lamb - Hopedale MA
John E. McNamara - Maynard MA
Assignee:
Stratus Computer, Inc. - Marlboro MA
International Classification:
G06F 1300
G06F 1342
US Classification:
364200
Abstract:
A fault-tolerant digital data processing system comprises at least a first input/output controller communicating with at least one peripheral device over a peripheral device bus. The peripheral bus includes first and second input/output buses, each having means for carrying data, address, control, and timing signals. The input/output controller includes an element for applying duplicate information signals synchronously and simultaneously to the first and second input/output buses for transfer to the peripheral device. The input/output controller further includes a bus interface element for receiving, in the absence of fault, duplicative information signals synchronously and simultaneously from the first and second input/output buses.
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Kurt F Baty from Austin, TX, age ~71 Get Report