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Kun W Hou

from San Jose, CA
Age ~49
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Related to:
Hong Pao Murphy, 64Hong Ping Hou, 67Quan Zhou Guo, 81Dao Hou Hong, 66Xiaohong Wang, 70
Connected to:
Aiting Hou, 46Alpha L Hou, 71Andrea Hou, 30Bin Hou, 61Bonnie S Hou, 56Buntha HouChi C Hou, 69Chris Hou, 53Christine A Hou, 37Clare Hou, 37

Kun Hou Phones & Addresses

  • 1133 Rajkovich Way, San Jose, CA 95120
  • Milpitas, CA
  • Albany, NY
  • Williamsburg, VA
  • Santa Clara, CA
  • 848 Towne Dr, Milpitas, CA 95035 (408) 449-5299

Publications

Us Patents

3D Polysilicon Diode With Low Contact Resistance And Method For Forming Same

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US Patent:
8410582, Apr 2, 2013
Filed:
May 23, 2012
Appl. No.:
13/479093
Inventors:
Abhijit Bandyopadhyay - San Jose CA, US
Kun Hou - Milpitas CA, US
Steven Maxwell - Synnyvale CA, US
Assignee:
SanDisk 3D LLC - Milpitas CA
International Classification:
H01L 29/66
US Classification:
257656
Abstract:
A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

In-Situ Passivation Methods To Improve Performance Of Polysilicon Diode

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US Patent:
8450181, May 28, 2013
Filed:
Jan 8, 2010
Appl. No.:
12/654927
Inventors:
Xiying Chen - San Jose CA, US
Kun Hou - Milpitas CA, US
Chuanbin Pan - San Jose CA, US
Abhijit Bandyopadhyay - San Jose CA, US
Yung-Tin Chen - Santa Clara CA, US
Assignee:
SanDisk 3D LLC - Milpitas CA
International Classification:
H01L 29/68
H01L 21/02
H01L 21/329
US Classification:
438381, 438478
Abstract:
A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.

3D Polysilicon Diode With Low Contact Resistance And Method For Forming Same

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US Patent:
8207064, Jun 26, 2012
Filed:
Sep 17, 2009
Appl. No.:
12/562079
Inventors:
Abhijit Bandyopadhyay - San Jose CA, US
Kun Hou - Milpitas CA, US
Steven Maxwell - Sunnyvale CA, US
Assignee:
SanDisk 3D LLC - Milpitas CA
International Classification:
H01L 21/44
US Classification:
438683, 438682
Abstract:
A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

Coated Carbon Nanoflakes

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US Patent:
20110175038, Jul 21, 2011
Filed:
Jan 26, 2009
Appl. No.:
12/359435
Inventors:
Kun Hou - Milpitas CA, US
Dennis M. Manos - Williamsburg VA, US
Ronald A. Outlaw - Williamsburg VA, US
International Classification:
H01B 1/04
H01B 1/02
B05D 5/12
B05D 3/10
B82Y 30/00
B82Y 40/00
US Classification:
252504, 252506, 252502, 252509, 427 77, 977775, 977890
Abstract:
Compositions of carbon nanoflakes are coated with a low Z compound, where an effective electron emission of the carbon nanoflakes coated with the low Z compound is improved compared to an effective electron emission of the same carbon nanoflakes that are not coated with the low Z compound or of the low Z compound that is not coated onto the carbon nanoflakes. Compositions of chromium oxide and molybdenum carbide-coated carbon nanoflakes are also described, as well as applications of these compositions. Carbon nanoflakes are formed and a low Z compound coating, such as a chromium oxide or molybdenum carbide coating, is formed on the surfaces of carbon nanoflakes. The coated carbon nanoflakes have excellent field emission properties.

Memory Cell That Employs A Selectively Fabricated Carbon Nano-Tube Reversible Resistance-Switching Element And Methods Of Forming The Same

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US Patent:
20120001150, Jan 5, 2012
Filed:
Sep 18, 2011
Appl. No.:
13/235409
Inventors:
April D. Schricker - Palo Alto CA, US
Wu-Yi Chien - San Jose CA, US
Kun Hou - Milpitas CA, US
Raghuveer S. Makala - Sunnyvale CA, US
Jingyan Zhang - Santa Clara CA, US
Yibo Nian - Palo Alto CA, US
International Classification:
H01L 29/16
H01L 21/20
B82Y 40/00
B82Y 99/00
US Classification:
257 9, 438384, 977842, 977742, 257E2109, 257E29082
Abstract:
In some aspects, a method of fabricating a memory cell is provided that includes fabricating a steering element above a substrate, and fabricating a reversible-resistance switching element coupled to the steering element by selectively fabricating carbon nano-tube (“CNT”) material above the substrate, wherein the CNT material comprises a single CNT. Numerous other aspects are provided.

Counter Doping Compensation Methods To Improve Diode Performance

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US Patent:
20120074367, Mar 29, 2012
Filed:
Sep 28, 2010
Appl. No.:
12/892633
Inventors:
Xiying Costa - San Jose CA, US
Abhijit Bandyopadhyay - San Jose CA, US
Kun Hou - Milpitas CA, US
Brian Le - San Jose CA, US
Yung-Tin Chen - Santa Clara CA, US
International Classification:
H01L 45/00
H01L 21/02
US Classification:
257 2, 438382, 257E45001, 257E21004
Abstract:
A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.

Bipolar Storage Elements For Use In Memory Cells And Methods Of Forming The Same

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US Patent:
20120091418, Apr 19, 2012
Filed:
Oct 14, 2010
Appl. No.:
12/904770
Inventors:
Yung-Tin Chen - Santa Clara CA, US
Franz Kreupl - Mountain View CA, US
Steven Maxwell - Sunnyvale CA, US
Kun Hou - Milpitas CA, US
International Classification:
H01L 45/00
H01L 21/02
US Classification:
257 4, 438382, 257E45002, 257E21004
Abstract:
In some embodiments, a memory cell is provided that includes (1) a bipolar storage element formed from a metal-insulator-metal (MIM) stack including (a) a first conductive layer; (b) a reversible resistivity switching (RRS) layer formed above the first conductive layer; (c) a metal/metal oxide layer stack formed above the first conductive layer; and (d) a second conductive layer formed above the RRS layer and the metal/metal oxide layer stack; and (2) a steering element coupled to the storage element. Numerous other aspects are provided.

Memory Cells Having Storage Elements That Share Material Layers With Steering Elements And Methods Of Forming The Same

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US Patent:
20120091419, Apr 19, 2012
Filed:
Oct 14, 2010
Appl. No.:
12/905047
Inventors:
Yung-Tin Chen - Santa Clara CA, US
Chuanbin Pan - Sunnyvale CA, US
Andrei Mihnea - San Jose CA, US
Steven Maxell - Sunnyvale CA, US
Kun Hou - Milpitas CA, US
International Classification:
H01L 45/00
H01L 21/02
US Classification:
257 4, 257 2, 438381, 257E45002, 257E21003
Abstract:
In some embodiments, a memory cell is provided that includes a storage element formed from an MIM stack including (1) a first conductive layer; (2) an RRS layer formed above the first conductive layer; and (3) a second conductive layer formed above the RRS layer, at least one of the first and second conductive layers comprising a first semiconductor material layer. The memory cell includes a steering element coupled to the storage element, the steering element formed from the first semiconductor material layer of the MIM stack and one or more additional material layers. Numerous other aspects are provided.
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Kun W Hou from San Jose, CA, age ~49 Get Report