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Kouros S Azimi

from Center Valley, PA
Age ~63
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Also known as:
Kouros I
Phone and address:
3087 Broadmoor Dr, Center Valley, PA 18034
(610) 882-0449
Related to:
Hengameh Azimi
Connected to:
Akbar M Azimi, 67Akram Azimi, 50Farid Azimi, 52Fatemeh Azimi, 84Muhammad I Azimi, 54Naheed Azimi, 40Shabnam Azimi, 31Sima Azimi, 57Yasmin Azimi, 39Zahra Azimi, 40

Kouros Azimi Phones & Addresses

  • 3087 Broadmoor Dr, Center Valley, PA 18034 (610) 882-0449 (610) 882-3636
  • 3100 Muirfield Rd, Center Valley, PA 18034
  • 502 Benner Rd #102, Allentown, PA 18104
  • 1052 Harriman Ct #104, West Chester, PA 19380 (610) 363-5647
  • 219 Sugartown Rd #104, Wayne, PA 19087 (610) 363-5647
  • Norristown, PA
  • Lehighton, PA
  • 3087 Broadmoor Dr, Center Valley, PA 18034

Work

Company: Bell semiconductor Feb 2019 Position: Senior director, ip

Education

Degree: High school graduate or higher

Skills

Analog Circuit Design • Mixed Signal Ic Design • Patents • Intellectual Property • Brainstorm Facilitation • Idea Generation • Ic • Semiconductors • Licensing • Asic • Vlsi • Soc • Digital Signal Processors • Analog • Cmos • Verilog • Debugging • Physical Design • Electronics • Semiconductor Industry • Rf • Facilitators • Hardware Architecture • Integrated Circuit Design • Facilitation • Eda • Mixed Signal • Patent Law

Industries

Legal Services

Resumes

Resumes

Kouros Azimi Photo 1

Senior Director, Ip

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Location:
Allentown, PA
Industry:
Legal Services
Work:
Bell Semiconductor
Senior Director, Ip
Independent Advisor
Independent Advisor
Anaqua Nov 2016 - Jul 2017
Director, Client Success
Avago Technologies May 2014 - Sep 2016
Director of Intellectual Property
Lsi Corporation/Avago Technologies May 2013 - May 2014
Director of Patent Development
Skills:
Analog Circuit Design
Mixed Signal Ic Design
Patents
Intellectual Property
Brainstorm Facilitation
Idea Generation
Ic
Semiconductors
Licensing
Asic
Vlsi
Soc
Digital Signal Processors
Analog
Cmos
Verilog
Debugging
Physical Design
Electronics
Semiconductor Industry
Rf
Facilitators
Hardware Architecture
Integrated Circuit Design
Facilitation
Eda
Mixed Signal
Patent Law

Publications

Us Patents

Frequency Selection Using Capacitance Multiplication

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US Patent:
7199651, Apr 3, 2007
Filed:
Nov 18, 2004
Appl. No.:
10/990368
Inventors:
Kouros Azimi - Center Valley PA, US
Thaddeus John Gabara - Murray Hill NJ, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03B 1/00
US Classification:
327552, 327156, 327147
Abstract:
A variable capacitance circuit on an integrated circuit comprises a MOS transistor, and a capacitance multiplier connected to one end of a channel of the MOS device. A MOS device is formed in series with an inductance, and a capacitance multiplier is formed to be connected to a node between the MOS device and the inductance.

Method And Apparatus For Disabling An Integrated Circuit (Ic) When An Attempt Is Made To Bypass Security On The Ic

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US Patent:
7202782, Apr 10, 2007
Filed:
Aug 4, 2004
Appl. No.:
10/911176
Inventors:
Kultaransingh N. Hooghan - Allentown PA, US
James T. Cargo - Bethlehem PA, US
Charles W. Berthoud - Bethlehem PA, US
Scott W. McLellan - Kempton PA, US
Kouros Azimi - Center Valley PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G08B 13/26
US Classification:
340561, 3405681, 3405686, 340571, 257679, 257922
Abstract:
The present invention provides an apparatus and method for detecting if a person has attempted to tamper with an integrated circuit (IC). The apparatus is located on the IC and comprises detection circuitry that detects a build up of electrical charge on the IC and disablement circuitry that disables the IC when the detection circuitry detects a build up of electrical charge on the IC. The method comprises detecting if a build up of electrical charge on the IC has occurred and disabling the IC when a build up of electrical charge on the IC has been detected.

Integrated Circuit Device Incorporating Metallurigical Bond To Enhance Thermal Conduction To A Heat Sink

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US Patent:
7327029, Feb 5, 2008
Filed:
Sep 27, 2005
Appl. No.:
11/235920
Inventors:
Kouros Azimi - Center Valley PA, US
Daniel Patrick Chesire - Winter Garden FL, US
Warren K Gladden - Macungie PA, US
Seung H. Kang - Sinking Spring PA, US
Taeho Kook - Orlando FL, US
Sailesh M. Merchant - Macungie PA, US
Vivian Ryan - Hampton NJ, US
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
H01L 23/34
US Classification:
257719, 257720, 257E23101, 257E23106, 438122
Abstract:
An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Integrated Circuit Device Incorporating Metallurgical Bond To Enhance Thermal Conduction To A Heat Sink

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US Patent:
7429502, Sep 30, 2008
Filed:
Oct 8, 2007
Appl. No.:
11/868624
Inventors:
Kouros Azimi - Center Valley PA, US
Daniel Patrick Chesire - Winter Garden FL, US
Warren K Gladden - Macungie PA, US
Seung H. Kang - Sinking Spring PA, US
Taeho Kook - Orlando FL, US
Sailesh M. Merchant - Macungie PA, US
Vivian Ryan - Hampton NJ, US
Assignee:
Agere Systems, Inc. - Allentown PA
International Classification:
H01L 21/00
US Classification:
438122, 257E23101, 257719, 257720, 257E23106
Abstract:
An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Method And Apparatus For Detecting And Adjusting Characteristics Of A Signal

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US Patent:
7696800, Apr 13, 2010
Filed:
Feb 5, 2008
Appl. No.:
12/012758
Inventors:
Kouros Azimi - Center Valley PA, US
Mohammad S. Mobin - Orefield PA, US
Gregory W. Sheets - Breinigsville PA, US
Lane A. Smith - Easton PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03K 5/12
US Classification:
327170, 327108
Abstract:
Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e. g. , a wire, a backplane, etc. ). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.

Method And Apparatus For Regulating A Power Supply Of An Integrated Circuit

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US Patent:
7791368, Sep 7, 2010
Filed:
Feb 5, 2008
Appl. No.:
12/012733
Inventors:
Kouros Azimi - Center Valley PA, US
Mohammad S. Mobin - Orefield PA, US
Gregory W. Sheets - Breinigsville PA, US
Lane A. Smith - Easton PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03K 17/16
H03K 19/003
US Classification:
326 33, 326 32, 326 34
Abstract:
Disclosed is a circuit for adjusting a voltage supplied to an IC by a power supply. The circuit includes a PVT detector configured to generate a control signal and an adjustable resistance device configured to adjust its resistance in response to the control signal.

Power Learning Security In Wireless Routers

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US Patent:
7948914, May 24, 2011
Filed:
Jan 28, 2009
Appl. No.:
12/322028
Inventors:
Kouros Azimi - Center Valley PA, US
Mohammad Mobin - Orefield PA, US
Roger Fratti - Mohnton PA, US
Sailesh Merchant - Macungie PA, US
Kenneth Paist - Spring City PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G01R 31/08
US Classification:
370252, 370318, 4554221
Abstract:
In described embodiments, elements of a wireless home network employ learned power security for the network. An access point, router, or other wireless base station emits and receives signals having corresponding signal strengths. Wireless devices coupled to the base station through a radio link are moved through the home network at boundary points of the home and the signal strength is measured at each device and communicated to the base station. Based on the signal strength information from the emitted signals measured at the boundary points and/or from measured signal strength information of signals received from the boundary points, the base station determines a network secure area. The base station declines permission of devices attempting to use or join the home network that exhibit signal strength characteristics less than boundary values for the network secure area.

Method And Apparatus For Detecting And Adjusting Characteristics Of A Signal

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US Patent:
7977989, Jul 12, 2011
Filed:
Mar 24, 2010
Appl. No.:
12/730671
Inventors:
Kouros Azimi - Center Valley PA, US
Mohammad S. Mobin - Orefield PA, US
Gregory W. Sheets - Breinigsville PA, US
Lane A. Smith - Easton PA, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03K 5/12
US Classification:
327170
Abstract:
Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e. g. , a wire, a backplane, etc. ). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the signal many times after a threshold voltage is applied to the latch. The circuit also includes a processor that determines the characteristic of the signal when the sampled voltages indicate a transition point and that adjusts the threshold voltage when the sampled voltages do not indicate a transition point. The processor adjusts the characteristic of the signal by adjusting at least one of a current and a voltage of the transmitter when the characteristic of the signal is outside a predetermined range.
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Kouros S Azimi from Center Valley, PA, age ~63 Get Report