Resumes
Resumes
Cpu Micro Architecture Researcher And Fpga Design
View pageLocation:
Canby, OR
Industry:
Computer Hardware
Work:
Caldera Development Group Aug 2019 - Nov 2019
Rtl Design Engineer
Physio-Control, Now Part of Stryker Nov 2017 - Jun 2018
Fpga Engineer
Hdlexpress.com May 2015 - Nov 2017
Cpu Micro Architecture Researcher and Fpga Design Engineer
Innovasic Semiconductor Feb 2015 - Apr 2015
Contract Fpga Design Engineer
Ossia Inc. Oct 2012 - Oct 2014
Verilog Rtl Design Engineer
Rtl Design Engineer
Physio-Control, Now Part of Stryker Nov 2017 - Jun 2018
Fpga Engineer
Hdlexpress.com May 2015 - Nov 2017
Cpu Micro Architecture Researcher and Fpga Design Engineer
Innovasic Semiconductor Feb 2015 - Apr 2015
Contract Fpga Design Engineer
Ossia Inc. Oct 2012 - Oct 2014
Verilog Rtl Design Engineer
Education:
Walla Walla University 1979 - 1982
Bachelors, Bachelor of Science In Electrical Engineering, Electronics Engineering, Electronics Collegedale Academy
Walla Walla University
Bachelors, Bachelor of Science, Electrical Engineering
Bachelors, Bachelor of Science In Electrical Engineering, Electronics Engineering, Electronics Collegedale Academy
Walla Walla University
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Fpga
Verilog
Debugging
Xilinx
Rtl Design
Modelsim
Simulations
Xilinx Ise
Embedded Software
Embedded Systems
Altera
Electrical Engineering
Hardware
Quartus
Electronics
Firmware
Digital Signal Processing
Cadence
Assembly Language
C (Programming Language
System Verilog
Mentor Questa Cdc Formal
Chipscope Pro
Signal Tap
Bluepearl Cdc Sw
Mentoring New Hires
System on A Chip
System Architecture
Micro Architecture
Risc V Isa Implemetation In A Cpu
Questasim
Assertion Based Verification
Functional Verification
Static Timing Analysis
Digital Circuit Design
Xilinx Vivado
Rtl Coding
Risc V Cpu Design
Cpu Design
Amateur Radio
Microarchitecture
Chipscope
Place and Route
Logic Synthesis
Systemverilog
Verilog
Debugging
Xilinx
Rtl Design
Modelsim
Simulations
Xilinx Ise
Embedded Software
Embedded Systems
Altera
Electrical Engineering
Hardware
Quartus
Electronics
Firmware
Digital Signal Processing
Cadence
Assembly Language
C (Programming Language
System Verilog
Mentor Questa Cdc Formal
Chipscope Pro
Signal Tap
Bluepearl Cdc Sw
Mentoring New Hires
System on A Chip
System Architecture
Micro Architecture
Risc V Isa Implemetation In A Cpu
Questasim
Assertion Based Verification
Functional Verification
Static Timing Analysis
Digital Circuit Design
Xilinx Vivado
Rtl Coding
Risc V Cpu Design
Cpu Design
Amateur Radio
Microarchitecture
Chipscope
Place and Route
Logic Synthesis
Systemverilog
Interests:
Dsp Design For Ham Radio
Education
Education
Kirk Weedman Canby, OR
View pageWork:
Ossia (www.ossiainc.com
Redmond, WA
Oct 2012 to Oct 2014
Western Digital
Longmont, CO
Apr 2012 to May 2012
Microsoft
Redmond, WA
Jul 2010 to Aug 2011
www.OPENHPSDR.ORG
Nov 2008 to Apr 2010
Teseda
Portland, OR
Jan 2003 to Feb 2008
Senior Hardware Design Engineer
Verilog RTL & Behavioral
Ottawa, ON
Mar 2001 to Dec 2002
Contract Design Engineer
Xerox/Tektronix Inc
Wilsonville, OR
Apr 1992 to Mar 2001
Senior Hardware/Software Design Engineer
Mannesmann Tally
Kent, WA
Jan 1988 to Apr 1992
Controller
Telex Computer Products
Tulsa, OK
Jan 1987 to Dec 1987
Flight Safety International
Tulsa, OK
May 1984 to Jan 1987
Teltronics
Lakeland, FL
Feb 1983 to May 1984
Redmond, WA
Oct 2012 to Oct 2014
Western Digital
Longmont, CO
Apr 2012 to May 2012
Microsoft
Redmond, WA
Jul 2010 to Aug 2011
www.OPENHPSDR.ORG
Nov 2008 to Apr 2010
Teseda
Portland, OR
Jan 2003 to Feb 2008
Senior Hardware Design Engineer
Verilog RTL & Behavioral
Ottawa, ON
Mar 2001 to Dec 2002
Contract Design Engineer
Xerox/Tektronix Inc
Wilsonville, OR
Apr 1992 to Mar 2001
Senior Hardware/Software Design Engineer
Mannesmann Tally
Kent, WA
Jan 1988 to Apr 1992
Controller
Telex Computer Products
Tulsa, OK
Jan 1987 to Dec 1987
Flight Safety International
Tulsa, OK
May 1984 to Jan 1987
Teltronics
Lakeland, FL
Feb 1983 to May 1984
Education:
Walla Walla University
1983
BSEE
1983
BSEE