Resumes
Resumes
Kirk Prall Phones & Addresses
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Angola, IN
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Caledonia, MI
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Wyoming, MI
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2307 Grassy Branch Dr, Meridian, ID 83642 (208) 884-3355
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Englewood, CO
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Billings, MT
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Boise, ID
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5922 Tumbleweed Dr SW, Grandville, MI 49418 (208) 884-3355
Work
Position:
Craftsman/Blue Collar
Education
Degree:
Associate degree or higher
Publications
Us Patents
Method Of Forming Flash Memory
View pageUS Patent:
6337244, Jan 8, 2002
Filed:
Mar 1, 2000
Appl. No.:
09/516818
Inventors:
Kirk D. Prall - Boise ID
Guy T. Blalock - Boise ID
Guy T. Blalock - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21336
US Classification:
438257, 438241, 438710, 216 79
Abstract:
A method of forming a line of FLASH memory cells includes forming a first line of floating gates over a crystalline silicon semiconductor substrate. An alternating series of SiO isolation regions and active areas are provided in the semiconductor substrate in a second line adjacent and along at least a portion of the first line of floating gates. The series of active areas define discrete transistor source areas. A masking layer is formed over the floating gates, the regions and the areas. A third line mask opening is formed in the masking layer over at least a portion of the second line. Anisotropic etching is conducted of the SiO isolation regions exposed through the third line mask opening substantially selectively relative to crystalline silicon exposed through the third line mask opening using a gas chemistry comprising a combination of at least one non-hydrogen containing fluorocarbon having at least three carbon atoms and at least one hydrogen containing fluorocarbon. The isolation regions are preferably formed in trenches previously etched into the crystalline silicon comprising semiconductor substrate. The anisotropic etching preferably removes substantially all of the third line opening exposed isolation regions.
Semiconductor-On-Insulator Transistor And Memory Circuitry Employing Semiconductor-On-Insulator Transistors
View pageUS Patent:
6404008, Jun 11, 2002
Filed:
May 20, 1999
Appl. No.:
09/315900
Inventors:
Kirk Prall - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 27108
US Classification:
257330, 257296, 257347
Abstract:
The invention includes several aspects related to semiconductor-on-insulator transistors, to memory and other DRAM circuitry and arrays, to transistor gate arrays, and to methods of fabricating such constructions. In one aspect, a semiconductor-on-insulator transistor includes, a) an insulator layer; b) a layer of semiconductor material over the insulator layer; c) a transistor gate provided within the semiconductor material layer; and d) an outer elevation source/drain diffusion region and an inner elevation diffusion region provided within the semiconductor material layer in operable proximity to the transistor gate. In another aspect, DRAM circuitry includes a plurality of memory cells not requiring sequential access, at least a portion of the plurality having more than two memory cells for a single bit line contact. In still another aspect, a DRAM array of memory cells comprises a plurality of wordlines, source regions, drain regions, bit lines in electrical connection with the drain regions, and storage capacitors in electrical connection with the source regions; at least two drain regions of different memory cells being interconnected with one another beneath one of the wordlines. In yet another aspect, a DRAM array has more than two memory cells for a single bit line contact, and a plurality of individual memory cells occupy a surface area of less than or equal to 2fÃ(2f+f/N), where âfâ is the minimum photolithographic feature size with which the array was fabricated, and âNâ is the number of memory cells per single bit line contact within the portion.
Reduced Leakage Dram Storage Unit
View pageUS Patent:
6404669, Jun 11, 2002
Filed:
Dec 18, 2000
Appl. No.:
09/739850
Inventors:
Zhigiang Wu - Meridian ID
Randhir PS Thakur - Boise ID
Alan Reinberg - Boise ID
Kirk Prall - Boise ID
Randhir PS Thakur - Boise ID
Alan Reinberg - Boise ID
Kirk Prall - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1134
US Classification:
365149, 365174, 365175, 365177
Abstract:
The present invention is directed to a memory cell which comprises a storage node, a switching device for controlling access to the storage node, and a diode between the switching device and the storage node. A method for controlling charge transfer to and from a storage node through a switching device is also disclosed.
Method Of Forming Flash Memory, Method Of Forming Flash Memory And Sram Circuitry, And Etching Methods
View pageUS Patent:
6406959, Jun 18, 2002
Filed:
Jan 4, 1999
Appl. No.:
09/225893
Inventors:
Kirk D. Prall - Boise ID
Gregg Rettschlag - Boise ID
Graham Wolstenholme - Boise ID
Gregg Rettschlag - Boise ID
Graham Wolstenholme - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 218247
US Classification:
438258
Abstract:
In one implementation, a method of forming an array of FLASH memory includes forming a plurality of lines of floating gates extending from a memory array area to a peripheral circuitry area over a semiconductor substrate. In a common masking step, discrete openings are formed over a) at least some of the lines of floating gates in the peripheral circuitry area, and b) floating gate source area in multiple lines along at least portions of the lines of floating gates within the memory array area. In one implementation, a line of floating gates is formed over a semiconductor substrate. A conductive line different from the line of floating gates is formed over the semiconductor substrate. In a common masking step, discrete openings are formed to a) at least one of the conductive line and the line of floating gates, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates. In one implementation, a method of forming FLASH memory and SRAM circuitry includes forming a line of floating gates over a semiconductor substrate and an SRAM gate over the semiconductor substrate. In a common masking step, discrete openings are formed over a) the SRAM gate, and b) floating gate source area of multiple transistors comprising the line of floating gates along at least a portion of the line of floating gates.
Formation Of Silicided Contact By Ion Implantation
View pageUS Patent:
6406998, Jun 18, 2002
Filed:
Feb 5, 1996
Appl. No.:
08/596613
Inventors:
Kirk D. Prall - Boise ID
Gurtej S. Sandhu - Boise ID
Gurtej S. Sandhu - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2144
US Classification:
438659, 438660, 438664, 438668, 438672, 438675, 438692, 438745, 438756
Abstract:
Disclosed is a method using the implantation of ionized titanium for the formation of an electrical contact having a metal silicide diffusion barrier. The electrical contact is created by the steps of etching a contact opening over an active region on an in-process integrated circuit wafer, implanting metal ions into the contact opening, and annealing the contact opening to form a titanium silicide layer at the bottom of the contact opening adjacent to the underlying active region. In a further step, a titanium nitride layer is formed on the surface of the contact opening above the metal silicide layer, and the remainder of the contact opening is then filled by depositing tungsten into the contact opening. The method is especially useful for forming contacts having a high aspect ratio and for forming self-aligned contacts as it is capable of forming a uniform silicide layer at the bottom of a narrow contact opening.
Method For Forming A Semiconductor Connection With A Top Surface Having An Enlarged Recess
View pageUS Patent:
6426287, Jul 30, 2002
Filed:
Jul 11, 2001
Appl. No.:
09/903338
Inventors:
Guy Blalock - Boise ID
Kirk Prall - Boise ID
Fernando Gonzalez - Boise ID
Kirk Prall - Boise ID
Fernando Gonzalez - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21476
US Classification:
438629, 438456, 438672, 438673, 438701, 438703, 438713
Abstract:
A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.
Method For Forming A Semiconductor Connection With A Top Surface Having An Enlarged Recess
View pageUS Patent:
6429526, Aug 6, 2002
Filed:
May 12, 1999
Appl. No.:
09/310649
Inventors:
Guy Blalock - Boise ID
Kirk Prall - Boise ID
Fernando Gonzalez - Boise ID
Kirk Prall - Boise ID
Fernando Gonzalez - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 2348
US Classification:
257774, 257751, 257753, 257768
Abstract:
A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.
Flash Memory With Overerase Protection
View pageUS Patent:
6442066, Aug 27, 2002
Filed:
Aug 28, 2001
Appl. No.:
09/940979
Inventors:
Kirk D. Prall - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 1604
US Classification:
36518501, 36518529
Abstract:
A non-volatile memory is described which includes an array of memory cells arranged in rows and columns. A split source line architecture is implemented and uses isolation transistors located throughout the memory array to couple selected memory cells in response to an active row line signal. The isolation transistors can be provided for each row of the memory array or for a pre-determined number of memory cells, such as 8, 16 or 32. By providing a split source line and isolation transistors, read errors caused by over erased memory cells can be eliminated with minimal increase in die area.