Kim Dang

54539986, Sep 26, 1995

Apr 26, 1993

8/053052

Kim C. Dang - Orange CA

Unisys Corporation - Blue Bell PA

G06F 1110
H03M 1300
G08C 2500
H04L 100

371 511

An array processing circuit which operates on a M row-N column array of digital words includes a first set of N memories, each of which asynchronously receives a respective column of words from a separate input channel; and, a second set of N memories which have respective inputs that are coupled to corresponding outputs of the first set of memories. A first addressing circuit detects when each memory of the first set contains a respective word of the same row, and in response transfers that row of words in parallel to the second set of memories. N-1 column error detect circuits respectively detect when a column of words from the first N-1 memories of the first set has an error. And, when only the i-th one of those error circuits detects an error, a second addressing circuit--a) sequentially reads words from each of the memories 1 thru i-1 of the second set, b) reads words from all N of the second set of memories in parallel, c) sequentially reads words from each of the memories i+1 thru N-1 of the second set; and then, repeats the reading sequence a) thru c) until all of the words in the array are read. Also, the array processing circuit includes up to seven other detailed circuit features.