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Khurram C Zafar

from San Jose, CA
Age ~56

Khurram Zafar Phones & Addresses

  • 3724 Morrie Dr, San Jose, CA 95127
  • 1363 Joyner Ct, San Jose, CA 95131
  • 179 Brandt Ct, Milpitas, CA 95035
  • Dallas, TX
  • Irving, TX
  • Richardson, TX

Work

Company: Anchor semiconductor Jun 2014 Position: Vice president of apps and technical marketing

Education

Degree: Masters School / High School: Southern Methodist University 1992 to 1992 Specialities: Computer Science

Skills

Semiconductors • Debugging • Engineering Management • Software Engineering • Embedded Systems • Product Development • Algorithms • Linux • Perl • Clearcase • Software Development • Embedded Software • C# • System Architecture • Eda • High Performance Computing • Rapid Prototyping • Semiconductor Industry • Usability • Ic • Multithreading

Languages

English

Interests

Exercise • Electronics • Home Improvement • Reading • Music • Sports • Automobiles • Movies • Home Decoration

Industries

Semiconductors

Resumes

Resumes

Khurram Zafar Photo 1

Vice President Of Apps And Technical Marketing

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Location:
3724 Morrie Dr, San Jose, CA 95127
Industry:
Semiconductors
Work:
Anchor Semiconductor
Vice President of Apps and Technical Marketing

Kla-Tencor Jan 2006 - May 2014
Principal Engineer

Kla-Tencor Jul 2004 - Dec 2005
Program Manager

Kla-Tencor Nov 1998 - Jun 2004
Engineering Manager

Texas Instruments Jun 1990 - Oct 1998
Software Engineer
Education:
Southern Methodist University 1992 - 1992
Masters, Computer Science
Rensselaer Polytechnic Institute 1986 - 1990
Bachelors, Bachelor of Science, Engineering
Skills:
Semiconductors
Debugging
Engineering Management
Software Engineering
Embedded Systems
Product Development
Algorithms
Linux
Perl
Clearcase
Software Development
Embedded Software
C#
System Architecture
Eda
High Performance Computing
Rapid Prototyping
Semiconductor Industry
Usability
Ic
Multithreading
Interests:
Exercise
Electronics
Home Improvement
Reading
Music
Sports
Automobiles
Movies
Home Decoration
Languages:
English

Publications

Isbn (Books And Publications)

Essential Wap for Web Professionals

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Author

Khurram Zafar

ISBN #

0130925683

Us Patents

Methods And Systems For Utilizing Design Data In Combination With Inspection Data

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US Patent:
20070288219, Dec 13, 2007
Filed:
Nov 20, 2006
Appl. No.:
11/561659
Inventors:
Khurram Zafar - San Jose CA, US
Sagar Kekare - Plano TX, US
Ellis Chang - Saratoga CA, US
Allen Park - San Jose CA, US
Peter Rose - Boulder Creek CA, US
International Classification:
G06F 17/50
US Classification:
703014000
Abstract:
Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Methods And Systems For Utilizing Design Data In Combination With Inspection Data

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US Patent:
20090297019, Dec 3, 2009
Filed:
Aug 3, 2009
Appl. No.:
12/534547
Inventors:
Khurram Zafar - San Jose CA, US
Sagar Kekare - Plano TX, US
Ellis Chang - Saratoga CA, US
Allen Park - San Jose CA, US
Peter Rose - Boulder Creek CA, US
Assignee:
KLA-TENCOR TECHNOLOGIES CORPORATION - Milpitas CA
International Classification:
G06K 9/00
US Classification:
382145
Abstract:
Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Region Based Virtual Fourier Filter

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US Patent:
20120141013, Jun 7, 2012
Filed:
Aug 1, 2011
Appl. No.:
13/381696
Inventors:
Lisheng Gao - Morgan Hill CA, US
Kenong Wu - Davis CA, US
Allen Park - San Jose CA, US
Ellis Chang - Saratoga CA, US
Khurram Zafar - San Jose CA, US
Junqing Huang - Fremont CA, US
Ping Gu - Milpitas CA, US
Christopher Maher - Campbell CA, US
Grace H. Chen - Los Gato CA, US
Songnian Rong - San Jose CA, US
Assignee:
KLA-TENCOR CORPORATION - Milpitas CA
International Classification:
G06K 9/62
US Classification:
382149
Abstract:
The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.

Determining Design Coordinates For Wafer Defects

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US Patent:
20130064442, Mar 14, 2013
Filed:
Aug 31, 2012
Appl. No.:
13/601891
Inventors:
Ellis Chang - Saratoga CA, US
Michael J. Van Riet - Sunnyvale CA, US
Allen Park - San Jose CA, US
Khurram Zafar - San Jose CA, US
Santosh Bhattacharyya - San Jose CA, US
Assignee:
KLA-TENCOR CORPORATION - Milpitas CA
International Classification:
G06K 9/62
US Classification:
382149
Abstract:
Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

Pattern Centric Process Control

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US Patent:
20210326505, Oct 21, 2021
Filed:
Apr 5, 2021
Appl. No.:
17/222132
Inventors:
- Santa Clara CA, US
Khurram Zafar - San Jose CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Rong Lv - Shanghai, CN
Justin Chen - Milpitas CA, US
Abhishek Vikram - Santa Clara CA, US
Yuan Xu - Sunnyvale CA, US
Ping Zhang - Saratoga CA, US
International Classification:
G06F 30/3323
G06N 5/04
G03F 7/20
Abstract:
Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

Pattern Centric Process Control

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US Patent:
20200097621, Mar 26, 2020
Filed:
Nov 26, 2019
Appl. No.:
16/696554
Inventors:
- Santa Clara CA, US
Khurram Zafar - San Jose CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Rong Lv - Shanghai, CN
Justin Chen - Milpitas CA, US
Abhishek Vikram - Santa Clara CA, US
Yuan Xu - Sunnyvale CA, US
Ping Zhang - Saratoga CA, US
International Classification:
G06F 17/50
G03F 7/20
G06N 5/04
Abstract:
Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

Pattern Centric Process Control

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US Patent:
20180300434, Oct 18, 2018
Filed:
Apr 3, 2018
Appl. No.:
15/944080
Inventors:
- Santa Clara CA, US
Khurram Zafar - San Jose CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Rong Lv - Shanghai, CN
Justin Chen - Milpitas CA, US
Abhishek Vikram - Santa Clara CA, US
Yuan Xu - Sunnyvale CA, US
Ping Zhang - Saratoga CA, US
International Classification:
G06F 17/50
G06N 99/00
G06N 5/04
G03F 7/20
Abstract:
Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.
Khurram C Zafar from San Jose, CA, age ~56 Get Report