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Kevin A Chiarot

from Rock Tavern, NY
Age ~64
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Also known as:
Kevin Arthur Chiarot, Kevin C Chiarot, Hairot C Kevin, Kevin T
Phone and address:
560 Station Rd, Rock Tavern, NY 12575
(845) 496-7910
Related to:
Justin M ChiarotJonathan D Roberts, 36Jonathan D RobertsJulia Schaper, 38Bethany G Chiarot, 36Cheryl A Chiarot, 66Rachel E Chiarot, 40Justin M Chiarot, 38Sarah C Chiarot, 32Elizabeth R Chiarot, 30Christopher J Chiarot, 34
Connected to:
John Chiarpotti, 42Christopher R Chiarulli, 95Frank J Chiarulli, 72Luke A Chiaruttini, 35Alan M Chiasson, 64Alexis M Chiasson, 30Bertha L Chiasson, 59Brent T Chiasson, 53Chad E Chiasson, 55France Chiasson, 52

Kevin Chiarot Phones & Addresses

  • 560 Station Rd, Rock Tavern, NY 12575 (845) 496-7910
  • 5664 Searsville Rd, Pine Bush, NY 12566
  • 17907 Hayworth Cv, Pflugerville, TX 78660 (512) 990-8158
  • 12 Beckford Cv, Jackson, TN 38305 (731) 660-6273 (731) 736-0053
  • Newburgh, NY
  • Poughkeepsie, NY
  • Austin, TX
  • Saugerties, NY
  • 12 Beckford Cv, Jackson, TN 38305 (731) 660-6273

Work

Position: Professional/Technical

Education

Degree: High school graduate or higher

Images

Specialities

Personal Injury • Bodily Injury • Insurance • Retail Risk

Professional Records

Lawyers & Attorneys

Kevin Chiarot Photo 1

Kevin Chiarot - Lawyer

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Office:
Whitelaw-Twining
Phone:
(604) 682-5466 (Phone), (866) 982-9898 (Phone), (604) 682-5217 (Fax)
Specialties:
Personal Injury
Bodily Injury
Insurance
Retail Risk
Memberships:
Canadian Bar Association; Law Society of Alberta; Law Society of British Columbia; Vancouver Bar Association
ISLN:
1001181634
Admitted:
2013
University:
University of Western Ontario, B.A., 2009
Law School:
The University of British Columbia, J.D., 2012
Links:
Site

Publications

Us Patents

Microprocessor Instruction Fetch Unit For Processing Instruction Groups Having Multiple Branch Instructions

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US Patent:
6622236, Sep 16, 2003
Filed:
Feb 17, 2000
Appl. No.:
09/506229
Inventors:
Kevin Arthur Chiarot - Pine Bush NY
Brian R. Konigsburg - Austin TX
Dave Stephen Levitan - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 930
US Classification:
712206, 712237, 712239
Abstract:
A microprocessor, data processing system, and an associated method of executing microprocessor instructions and generating instruction fetch addresses are disclosed. The microprocessor includes an instruction fetch unit comprising and instruction fetch address register (IFAR) and an instruction processing unit (IPU). The IFAR is configured to provide an address to an instruction cache. The IPU is suitable for receiving a set of instructions from the instruction cache and for generating an instruction fetch address upon determining from the set of instructions that the program execution flow requires redirection. The IPU is adapted to determine that the program flow requires redirection if the number of branch instructions in the set of instructions for which branch instruction information must be recorded exceeds the capacity of IPU to record the branch instruction information in a single cycle. The IPU may include an address generation unit suitable for generating a set of branch target addresses corresponding to the set of received instructions and a multiplexer configured to receive as inputs the set of branch target addresses. The output of the multiplexer is provided to the instruction address fetch register.

Recovery Mechanism For L1 Data Cache Parity Errors

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US Patent:
63321815, Dec 18, 2001
Filed:
May 4, 1998
Appl. No.:
9/072324
Inventors:
Douglas Craig Bossen - Austin TX
Kevin Arthur Chiarot - Pflugerville TX
Namratha Rajasekharaiah Jaisimha - Austin TX
Avijit Saha - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1208
G06F 1100
US Classification:
711155
Abstract:
A method of handling a cache error (such as a parity error), which allows a software recovery, by reporting the error using an unrelated system resource, such as an interrupt service, and particularly a data storage interrupt. The parity error can be reported by generating a data storage interrupt and using the data storage interrupt status register (DSISR) to indicate that the data storage interrupt is a result of the parity error. The context of the processor can be fully synchronized while handling the parity error.

Access Look-Aside Facility

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US Patent:
53903129, Feb 14, 1995
Filed:
Mar 23, 1994
Appl. No.:
8/216784
Inventors:
Kevin A. Chiarot - Poughkeepsie NY
Robert M. Dinkjian - Woodstock NY
Theodore J. Schmitt - Kingston NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
G06F 1210
G06F 1216
G06F 934
US Classification:
395400
Abstract:
An Access List Entry Token (ALET) access look-aside facility is used to look at all entries in the access Look-Aside Buffer (ALB) and select a Segment Table Destination (STD) for use in Dynamic Address Translation (DAT). At the same time that address generation is done to form the virtual address used for DAT, the content of the access register (i. e. , the ALET) to be used for the access is sent to the ALB. When the AR-specified STD is to be used for DAT, the ALET sent to the ALB is simultaneously compared with all the ALETs in the ALB. If the ALET compares with an ALET in an ALB entry, the STD associated with that entry is selected for use in the storage access.

Prefetching Instructions Between Caches

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US Patent:
57218641, Feb 24, 1998
Filed:
Sep 18, 1995
Appl. No.:
8/531948
Inventors:
Kevin Arthur Chiarot - Pflugerville TX
Michael John Mayfield - Austin TX
Era Kasturia Nangia - Austin TX
Milford John Peterson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1208
US Classification:
395464
Abstract:
A method for selectively pre-fetching Line M+1 into an L1 instruction cache from an L2 cache or from main memory during the execution of Line M. If unresolved branches exist in pending Line M, Line M+1 is speculative and may be pre-fetched into L1 instruction cache only from L2 cache, not from main memory. Unresolved branches in pending Line M are resolved before Line M+1 is pre-fetched from main memory. If no unresolved branches exist, Line M is committed ("inevitable-speculative") and is pre-fetched from main memory. In this way, no potentially wasteful pre-fetches are performed and main memory bandwidth is preserved.

Data Processing System Having An Apparatus For Out-Of-Order Register Operations And Method Therefor

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US Patent:
60617853, May 9, 2000
Filed:
Feb 17, 1998
Appl. No.:
9/024804
Inventors:
Kevin Arthur Chiarot - Pflugerville TX
A. James Van Norstrand - Round Rock TX
David Andrew Schroter - Round Rock TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1500
US Classification:
712236
Abstract:
An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.

Instruction Pre-Fetching Of A Cache Line Within A Processor

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US Patent:
58601503, Jan 12, 1999
Filed:
Oct 6, 1995
Appl. No.:
8/540374
Inventors:
Kevin Arthur Chiarot - Pflugerville TX
Michael John Mayfield - Austin TX
Era Kasturia Nangia - Austin TX
Milford John Peterson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711213
Abstract:
An apparatus for fetching data from a main memory into a primary cache memory of a processor. Instruction fetch requests are generated by the processor and assigned a priority level according to the predicted accuracy of the fetch request. The priority levels of different fetch requests are compared and the highest priority level fetch request is serviced first. An instruction cache line address N+1 is pre-fetched if there is a cache miss in the primary cache memory on address N+1.

Apparatus And Method For Tracking Out Of Order Load Instructions To Avoid Data Coherency Violations In A Processor

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US Patent:
6148394, Nov 14, 2000
Filed:
Feb 10, 1998
Appl. No.:
9/021134
Inventors:
Shih-Hsiung Stephen Tung - Austin TX
David Scott Ray - Georgetown TX
Kevin Arthur Chiarot - Pflugerville TX
Barry Duane Williamson - Round Rock TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9312
G06F 938
US Classification:
712218
Abstract:
The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocesor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists.

Directory Look-Aside Table For A Virtual Storage System Including Means For Minimizing Synonym Entries

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US Patent:
53197615, Jun 7, 1994
Filed:
Aug 12, 1991
Appl. No.:
7/744203
Inventors:
Kevin A. Chiarot - Poughkeepsie NY
Richard J. Schmalz - Wappinger Falls NY
Theodore J. Schmitt - Kingston NY
Arnold S. Tran - Shokan NY
Shih-Hsiung S. Tung - Kingston NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
395400
Abstract:
An improved DLAT structure distinguishes between address spaces and data spaces. The DLAT structure classifies data spaces by one or more space identifications which control assignment of virtual page addresses to DLAT rows. In one embodiment, a "private space bit" is used to select different DLAT addressing algorithms. In another embodiment, data spaces are sub-classified using space identification bits, and for each sub-class, a unique algorithm is selected based on the page address bits. An Exclusive OR function is used to generate the DLAT selection bits. This approach minimizes private space synonyms while maximizing common space synonyms. The result is improved performance since the former minimizes thrashing and the latter maximizes the value of the DLAT common bit.
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Kevin A Chiarot from Rock Tavern, NY, age ~64 Get Report