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Keone R Streicher

from Austin, TX
Age ~55

Keone Streicher Phones & Addresses

  • 3207 Twilight Trl, Austin, TX 78748 (925) 968-9038
  • Lahaina, HI
  • Wailuku, HI
  • 2976 Davidwood Way, San Jose, CA 95148
  • Milpitas, CA
  • San Ramon, CA
  • Corvallis, OR
  • Sunnyvale, CA
  • San Rafael, CA

Work

Position: Building and Grounds Cleaning and Maintenance Occupations

Education

Degree: Associate degree or higher

Publications

Us Patents

Programmable Clock Network For Distributing Clock Signals To And Between First And Second Sections Of An Integrated Circuit

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US Patent:
7228451, Jun 5, 2007
Filed:
Nov 8, 2005
Appl. No.:
11/270801
Inventors:
Triet Nguyen - San Jose CA, US
David Jefferson - Morgan Hill CA, US
Srinivas Reddy - Fremont CA, US
Keone Streicher - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 1/04
US Classification:
713500, 713503, 326 39
Abstract:
A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.

Fpga Configuration Bitstream Encryption Using Modified Key

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US Patent:
7606362, Oct 20, 2009
Filed:
Jan 25, 2005
Appl. No.:
11/042019
Inventors:
Keone Streicher - San Ramon CA, US
David Jefferson - Morgan Hill CA, US
Juju Joyce - Sunnyvale CA, US
Martin Langhammer - Wiltshire, GB
Assignee:
Altera Corporation - San Jose CA
International Classification:
H04L 21/00
US Classification:
380 29
Abstract:
Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.

Fpga Configuration Bitstream Protection Using Multiple Keys

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US Patent:
7725738, May 25, 2010
Filed:
Jan 25, 2005
Appl. No.:
11/042477
Inventors:
Martin Langhammer - Wiltshire, GB
Juju Joyce - Sunnyvale CA, US
Keone Streicher - San Ramon CA, US
David Jefferson - Morgan Hill CA, US
Srinivas Reddy - Fremont CA, US
Nitin Prasad - Bethesda MD, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 12/14
US Classification:
713191, 713194, 726 26, 380 44
Abstract:
Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.

Encryption Key Obfuscation And Storage

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US Patent:
7734043, Jun 8, 2010
Filed:
Jan 25, 2005
Appl. No.:
11/042032
Inventors:
David Jefferson - Morgan Hill CA, US
Martin Langhammer - Wiltshire, GB
Keone Streicher - San Ramon CA, US
Juju Joyce - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 9/00
H04K 1/00
G06F 9/24
US Classification:
380 37, 713 1, 713189
Abstract:
Circuits, methods, and apparatus that prevent easy detection and erasure or modification of an encryption or encoding key. This key may be used to encode and decode a configuration bitstream for an FPGA or other programmable or configurable device. One embodiment of the present invention obfuscates a key then stores it in a memory array on an FPGA. This memory array may be a one-time programmable memory to prevent erasure or modification of the key. After retrieval from storage, a reverse or de-obfuscation is performed to recover the key. Further obfuscation may be achieved by proper layout of the relevant circuitry.

One-Time Programmable Memories For Key Storage

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US Patent:
7818584, Oct 19, 2010
Filed:
Jan 25, 2005
Appl. No.:
11/042937
Inventors:
Juju Joyce - Sunnyvale CA, US
Martin Langhammer - Wiltshire, GB
Keone Streicher - San Ramon CA, US
David Jefferson - Morgan Hill CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 11/30
G06F 12/14
US Classification:
713189
Abstract:
Circuits, methods, and apparatus that store and prevent modification or erasure of stored encoding keys, serial identification numbers, or other information. An encoding key stored with an embodiment of the present invention may be used to decode a configuration bitstream on an integrated circuit, such as an FPGA. A serial number may be used to track or authenticate an integrated circuit. Embodiments of the present invention store this information in a memory such as an SRAM, DRAM, EPROM, EEPROM, flash, fuse array, or other type of memory. In order to prevent its erasure or modification, write enable circuitry for the memory is then permanently disabled, and if the memory is volatile, a continuous power supply is provided. Further refinements verify that the write enable circuitry has been disabled before allowing the device to be configured or to be operable.

Specialized Processing Block For Programmable Logic Device

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US Patent:
7836117, Nov 16, 2010
Filed:
Jul 18, 2006
Appl. No.:
11/458361
Inventors:
Martin Langhammer - Salisbury, GB
Kwan Yee Martin Lee - Hayward CA, US
Triet M. Nguyen - San Jose CA, US
Keone Streicher - San Ramon CA, US
Orang Azgomi - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 7/38
US Classification:
708603
Abstract:
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Fpga Configuration Bitstream Encryption Using Modified Key

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US Patent:
7984292, Jul 19, 2011
Filed:
Sep 14, 2009
Appl. No.:
12/559287
Inventors:
Keone Streicher - San Ramon CA, US
David Jefferson - Morgan Creek CA, US
Juju Joyce - Sunnyvale CA, US
Martin Langhammer - Salisbury, GB
Assignee:
Altera Corporation - San Jose CA
International Classification:
H04L 29/06
G06F 15/16
US Classification:
713160, 713161, 709236, 714100
Abstract:
Circuits, methods, and apparatus that prevent detection and erasure of a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a user key in order to prevent its detection. In a specific embodiment, the user key is masked by software that performs a function on it a first number of times. The result is used to encrypt a configuration bitstream. The user key is also provided to an FPGA or other device, where the function is performed a second number of times and the result stored. When the device is configured, the result is retrieved, the function is performed on it the first number of times less the second number of times and then it is used to decrypt the configuration bitstream. A further embodiment uses a one-time programmable fuse (OTP) array to prevent erasure or modification.

Specialized Processing Block For Programmable Logic Device

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US Patent:
8041759, Oct 18, 2011
Filed:
Jun 5, 2006
Appl. No.:
11/447370
Inventors:
Martin Langhammer - Alderbury, GB
Kwan Yee Martin Lee - Hayward CA, US
Orang Azgomi - Sunnyvale CA, US
Keone Streicher - San Ramon CA, US
Robert L. Pelt - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19/173
H01L 25/00
G06F 17/10
G06F 17/17
G06F 7/38
US Classification:
708523, 708501, 708301, 708313, 326 47, 326 38
Abstract:
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations, including finite impulse response (FIR) filters and infinite impulse response (IIR) filters. By using the programmable connections, and in some cases the programmable resources of the programmable logic device, and by running portions of the specialized processing block at higher clock speeds than the remainder of the programmable logic device, more complex FIR and IIR filters can be implemented.
Keone R Streicher from Austin, TX, age ~55 Get Report