Kenneth Conrad Bell

7071752, Jul 4, 2006

Jan 29, 2004

10/768365

Venkateswar R. Kowkutla - Plano TX, US
Shifeng Zhao - Dallas TX, US
Luis E. Ossa - Plano TX, US
Kenneth M. Bell - Windom TX, US
Anker Josefsen - Gentofte, DK
Lars Risbo - Copenhagen, DK

Texas Instruments Incorporated - Dallas TX

G06F 1/04

327291, 327299

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

20020060605, May 23, 2002

Aug 31, 2001

09/945027

Venkateswar Kowkutla - Plano TX, US
Shifeng Zhao - Dallas TX, US
Luis Ossa - Plano TX, US
Kenneth Bell - Windom TX, US
Anker Josefsen - Gentofte, DK
Lars Risbo - Kobenhavn, DK
Michael Tsecouras - Carrollton TX, US

H03F003/38

330/010000

A digital amplifier includes a noise shaper and a dither generator arranged to introduce noise to the shaper. The generator uses a seed value derived from a state variable of the shaper.

49390996, Jul 3, 1990

Sep 21, 1989

7/411210

Michael R. Seacrist - Grapevine TX
Joe R. Trogolo - Plano TX
Kenneth M. Bell - Windom TX

Texas Instruments Incorporated - Dallas TX

H01L 2980

437 31

A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).

43227384, Mar 30, 1982

Jan 21, 1980

6/113853

Kenneth M. Bell - Princeton TX
Joe R. Trogolo - Plano TX

Texas Instruments Incorporated - Dallas County TX

H01L 2980

357 22

A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.

44070055, Sep 27, 1983

Oct 5, 1981

6/308699

Kenneth M. Bell - Princeton TX
Joe R. Trogolo - Plano TX

Texas Instruments Incorporated - Dallas TX

H01L 2918

357 23

A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.

58924710, Apr 6, 1999

May 14, 1997

8/856497

Shivaling Mahant-Shetti - Garland TX
Kenneth M. Bell - Windom TX
Sami Kiriaki - Garland TX

Texas Instruments Incorporated - Dallas TX

H03M 166

341135

A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21. sub. 0 -21. sub. N-1 and 25. sub. 0 -25. sub. N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

20150222890, Aug 6, 2015

Apr 15, 2015

14/687109

- Taoyuan Hsien, TW
Harold BELLIS - Garland TX, US
Adam KUNZMAN - Allen TX, US
Kenneth BELL - Plano TX, US

H04N 13/04
H04N 13/00

A dual-channel three-dimension projector is provided. The dual-channel three-dimension projector comprises a video processor, an FPGA, a first driver, a second driver and a digital micromirror device (DMD). The video processor receives a first video data via a first input interface and a second video data via a second input interface to generate a left-eye signal and a right-eye signal. The FPGA receives the left-eye signal and the right-eye signal via two paths respectively, and generates a left-image signal and a right-image signal. The first driver receives the left-image signal to generate a left-image control signal. The second driver receives the right-image signal to generate a right-image control signal. The DMD electrically connected to the first driver and the second driver alternately projects a left-eye image and a right-eye image according to the left-image control signal and the right-image control signal.