Kedar Bhole Phones & Addresses
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10988 Ivy Hill Dr #6, San Diego, CA 92131
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5370 Toscana Way, San Diego, CA 92122 (858) 824-9279
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5220 Fiore Ter, San Diego, CA 92122 (858) 824-9279
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5255 Clairemont Mesa Blvd, San Diego, CA 92117 (858) 505-0689
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Temple City, CA
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Cupertino, CA
Education
Degree:
High school graduate or higher
Publications
Us Patents
Integrated Circuits (Ic) Employing Subsystem Shared Cache Memory For Facilitating Extension Of Low-Power Island (Lpi) Memory And Related Methods
View pageUS Patent:
20230029696, Feb 2, 2023
Filed:
Jul 30, 2021
Appl. No.:
17/390274
Inventors:
- San Diego CA, US
Subbarao Palacharla - San Diego CA, US
Jeffrey Shabel - San Diego CA, US
Isaac Berk - San Diego CA, US
Kedar Bhole - San Diego CA, US
Vipul Gandhi - San Diego CA, US
George Patsilaras - San Diego CA, US
Sparsh Singhai - San Diego CA, US
Subbarao Palacharla - San Diego CA, US
Jeffrey Shabel - San Diego CA, US
Isaac Berk - San Diego CA, US
Kedar Bhole - San Diego CA, US
Vipul Gandhi - San Diego CA, US
George Patsilaras - San Diego CA, US
Sparsh Singhai - San Diego CA, US
International Classification:
G06F 12/084
G06F 1/3212
G06F 1/3212
Abstract:
Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.
Method And Apparatus For Flexible Cache Partitioning By Sets And Ways Into Component Caches
View pageUS Patent:
20160019157, Jan 21, 2016
Filed:
Jul 17, 2014
Appl. No.:
14/333981
Inventors:
- San Diego CA, US
Moinul Khan - San Diego CA, US
Alain Artieri - San Diego CA, US
Kedar Bhole - San Diego CA, US
Vinod Chamarty - San Diego CA, US
Pankaj Chaurasia - Cupertino CA, US
Raghu Sankuratri - San Diego CA, US
Moinul Khan - San Diego CA, US
Alain Artieri - San Diego CA, US
Kedar Bhole - San Diego CA, US
Vinod Chamarty - San Diego CA, US
Pankaj Chaurasia - Cupertino CA, US
Raghu Sankuratri - San Diego CA, US
International Classification:
G06F 12/08
G06F 12/10
G06F 12/12
G06F 12/10
G06F 12/12
Abstract:
Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.
Method And Apparatus For A Shared Cache With Dynamic Partitioning
View pageUS Patent:
20160019158, Jan 21, 2016
Filed:
Jul 17, 2014
Appl. No.:
14/334010
Inventors:
- San Diego CA, US
Moinul Khan - San Diego CA, US
Alain Artieri - San Diego CA, US
Kedar Bhole - San Diego CA, US
Vinod Chamarty - San Diego CA, US
Yanru Li - San Diego CA, US
Raghu Sankuratri - San Diego CA, US
George Patsilaras - Del Mar CA, US
Pavan Kumar Thirunagari - Sunnyvale CA, US
Andrew Edward Turner - San Diego CA, US
Jeong-Ho Woo - San Diego CA, US
Moinul Khan - San Diego CA, US
Alain Artieri - San Diego CA, US
Kedar Bhole - San Diego CA, US
Vinod Chamarty - San Diego CA, US
Yanru Li - San Diego CA, US
Raghu Sankuratri - San Diego CA, US
George Patsilaras - Del Mar CA, US
Pavan Kumar Thirunagari - Sunnyvale CA, US
Andrew Edward Turner - San Diego CA, US
Jeong-Ho Woo - San Diego CA, US
International Classification:
G06F 12/08
Abstract:
Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.