Kayhan E Kucukcakar

6964027, Nov 8, 2005

Apr 16, 2003

10/417926

Kayhan Kucukcakar - Sunnyvale CA, US
Rachid N. Helaihel - Mountain View CA, US

Synopsys, Inc. - Mountain View CA

G06F017/50

716 2, 716 5, 716 6

A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redundant information, resolution of conflicting information, and other transformations. The new list allows more efficient timing analysis, synthesis, placement, routing, noise analysis, power analysis, reliability analysis, and other operations to be performed by EDA tools.

7506293, Mar 17, 2009

Mar 22, 2006

11/387224

Ali Dasdan - San Jose CA, US
Emre Salman - Istanbul, TR
Feroze P. Taraporevala - San Jose CA, US
Kayhan Kucukcakar - Sunnyvale CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 6, 716 4, 716 5, 703 14, 703 19

A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e. g. , 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e. g. , a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

7552409, Jun 23, 2009

Jun 7, 2005

11/147814

Kayhan Kucukcakar - Sunnyvale CA, US
Jing C. Lin - Cupertino CA, US
Jinan Lou - Cupertino CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 5, 716 6, 703 16

A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff tool, and more specifically, the signoff algorithm used by that tool is the most accurate model of actual IC behavior, the use of violation context data generated by the signoff tool to implement changes to the design layout will generally produce appropriate and effective results. By accessing this violation context data from the signoff tool, an implementation tool need not rely on its less accurate implementation analysis to determine the optimal design layout modifications for correcting violations detected by the signoff tool.

7650580, Jan 19, 2010

Dec 21, 2006

11/644563

Kayhan Kucukcakar - Sunnyvale CA, US
Ali Dasdan - San Jose CA, US
Halim Damerdji - Los Altos CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50
G06F 17/10
G06F 19/00
G01R 27/08
G01R 31/00

716 6, 703 2, 703 16, 702 83, 702118, 702179, 702180, 702181

A system that determines the performance of an integrated circuit (IC). During operation, the system receives probability distributions for parameters for the IC. Next, the system generates samples of the IC, wherein generating a given sample involves using the probability distribution to assign values to the parameters for components within the IC. The system then calculates output performance metrics for the samples based on the assigned values of the parameters, and uses the calculated output performance metrics to generate a distribution of output performance metrics for the samples.

7774731, Aug 10, 2010

Jul 17, 2008

12/175356

Ali Dasdan - San Jose CA, US
Emre Salman - Istanbul, TR
Feroze P. Taraporevala - Los Altos CA, US
Kayhan Kucukcakar - Sunnyvale CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 6, 716 4, 716 5, 703 14, 703 19

A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e. g. , 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e. g. , a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation.

8434040, Apr 30, 2013

Apr 27, 2011

13/095713

Sarvesh Bhardwaj - Fremont CA, US
Khalid Rahmat - Fremont CA, US
Kayhan Kucukcakar - Los Altos CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716108, 716113, 716134

A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.

8443328, May 14, 2013

Jun 14, 2010

12/815325

Florentin Dartu - Lake Oswego OR, US
Patrick D. Fortner - Beaverton OR, US
Kayhan Kucukcakar - Los Altos CA, US
Qiuyang Wu - Portland OR, US

Synopsys, Inc. - Mountain View CA

G06F 17/50
G06F 9/455

716134, 716108, 716113, 716122, 716136

A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block.

8615727, Dec 24, 2013

Dec 16, 2010

12/970812

Praveen Ghanta - Sunnyvale CA, US
Amit Goel - Santa Clara CA, US
Feroze P. Taraporevala - Los Altos CA, US
Marina Ovchinnikov - Saratoga CA, US
Jinfeng Liu - San Jose CA, US
Kayhan Kucukcakar - Los Altos CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716134

A method of performing simultaneous multi-corner static timing analysis (STA) on a design for an integrated circuit is provided. This method can include reading design data including a netlist, parasitics, and libraries at a plurality of corners. Each corner can represent a set of process, temperature, and voltage conditions. Using the design data as inputs, a plurality of operations can be performed to generate timing reports regarding the design at the plurality of corners. Notably, each operation has a single control flow and uses vectors of samples for performing the plurality of operations. Each sample is a value associated with a corner. This method minimizes computational resource and memory usage as well as accelerates the turn around time of multi-corner analysis.