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Kaushal K Agrawal

from San Jose, CA
Age ~59

Kaushal Agrawal Phones & Addresses

  • 7236 Saint George Ln, San Jose, CA 95120 (408) 229-8573 (408) 281-4267
  • 195 Avenida Espana, San Jose, CA 95139 (408) 229-8573
  • Washington, DC
  • 7236 Saint George Ln, San Jose, CA 95120 (408) 229-8573

Work

Company: Panasonic r&d - Cupertino, CA Jan 2012 Position: Interaction designer & tech lead

Education

School / High School: Carnegie Mellon University- Pittsburgh, PA 2011 Specialities: MHCI in Human Computer Interaction

Resumes

Resumes

Kaushal Agrawal Photo 1

Vp, Global Customer Service

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Location:
San Francisco, CA
Industry:
Telecommunications
Work:
Atrica
Vp, Global Customer Service
Kaushal Agrawal Photo 2

Vice President

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Location:
San Francisco, CA
Industry:
Telecommunications
Work:
Atrica
Vice President
Kaushal Agrawal Photo 3

Kaushal Agrawal

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Kaushal Agrawal Photo 4

Kaushal Agrawal New York, NY

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Work:
Panasonic R&D
Cupertino, CA
Jan 2012 to Aug 2012
Interaction Designer & Tech Lead

myfigments.com
Hyderabad, Andhra Pradesh
Jun 2010 to Jul 2011
Founder, Artist and Web Developer

Oracle
Hyderabad, Andhra Pradesh
Jun 2009 to Jul 2011
Member Technical Staff

Symantec
Pune, Maharashtra
Oct 2008 to Apr 2009
Project Intern

Education:
Carnegie Mellon University
Pittsburgh, PA
2011 to 2012
MHCI in Human Computer Interaction

Pune Institute of Computer Technology
Pune, Maharashtra
2005 to 2009
BE in Information Technology

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kaushal Agrawal
CTO
Atrica Inc.
Electrical Machinery, Equipment, and Supplies...
32553 Scott Blvd, Santa Clara, CA 95054
Kaushal Agrawal
CTO
Atrica Inc.
Electrical Machinery, Equipment, and Supplies...
32553 Scott Blvd, Santa Clara, CA 95054
Kaushal K. Agrawal
Principal
Atrica Inc
Nonclassifiable Establishments
7236 Saint George Ln, San Jose, CA 95120
Kaushal K. Agrawal
Interloq LLC
Nonclassifiable Establishments
7236 Saint George Ln, San Jose, CA 95120

Publications

Us Patents

Multipurpose Testing System For Optical Cross Connect Devices

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US Patent:
6959126, Oct 25, 2005
Filed:
Feb 8, 2002
Appl. No.:
10/072682
Inventors:
Rob Lofland - Sunnyvale CA, US
Kevin White - Los Gatos CA, US
Kaushal K. Agrawal - San Jose CA, US
Peter Hunt - Scotts Valley CA, US
Assignee:
Calient Networks - San Jose CA
International Classification:
G02B006/26
G02B006/42
US Classification:
385 16, 385 20, 385 24, 398 12, 398 19
Abstract:
A technique is disclosed for performing testing of an optical device under test (DUT). According to a specific embodiment, the DUT includes a plurality of DUT optical input ports and a plurality of DUT optical output ports. The testing may be performed by an optical switching testing system (OSTS) which includes a plurality of OSTS output ports optically connected to a plurality of DUT input ports, and a plurality of OSTS input ports optically connected to a plurality of DUT output ports. Components of the OSTS are configured in order to perform a specific test on the DUT. A first test scenario is configured at the DUT. At least one optical test signal is transmitted to at least one DUT input port. Test results may then be obtained by monitoring at least one DUT output port for the presence or absence of light. The test results are then analyzed for specific characteristics.

Automatic Statistical Test Sequence Generator And Methods Thereof

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US Patent:
6792377, Sep 14, 2004
Filed:
Jul 1, 2002
Appl. No.:
10/188211
Inventors:
Kaushal K. Agrawal - San Jose CA
David N. K. Wong - Milpitas CA
Assignee:
Calient Networks - San Jose CA
International Classification:
G06R 2728
US Classification:
702119, 702117, 714 33
Abstract:
A TL1 usage model generator arranged to provide a statistically accurate usage model based upon a particular user profile is described. The TL1 usage model generator is connected to a translator arranged to expand the usage model provided the by TL1 usage model generator into a fully meshed file. Coupled to the translator, a TL1 sequence generator uses the fully meshed file to automatically generate a random sequence of TL1 commands that is provided to an execution engine configured to read the random sequence of TL1 commands. The execution engine, in turn, sends the random sequence of TL1 commands to the system under test (SUT) the results of which are forwarded to and written in a result data base used by a post processor to verify the validity of the system response.
Kaushal K Agrawal from San Jose, CA, age ~59 Get Report