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Katen A Shah

from Folsom, CA
Age ~60
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Also known as:
Katen Ilse Shah, Katen I Shah, Katen Shaw, Kumar Shah Katen, Shah Katen, Shaw Katen
Phone and address:
1177 Penrod Way, Folsom, CA 95630
(916) 984-1232
Related to:
Dwight E Brown, 54Ilse C Shah, 61Carmen E Morales, 42
Connected to:
Aadit Shah, 32Aajay N Shah, 62Aarushi M Shah, 36Aayushi Shah, 29Abhi V Shah, 46Affan T Shah, 29Afifa Shah, 45Ajmal Shah, 32Akar J Shah, 34Akhtar Z Shah, 80

Katen Shah Phones & Addresses

  • 1177 Penrod Way, Folsom, CA 95630 (916) 984-1232
  • Orangevale, CA
  • Lincoln, NE
  • Sacramento, CA
  • 1177 Penrod Way, Folsom, CA 95630

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: Graduate or professional degree

Resumes

Resumes

Katen Shah Photo 1

President

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Work:
Katen Shah Design
President
Katen Shah Photo 2

Graphics Architect

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Location:
Sacramento, CA
Industry:
Semiconductors
Work:
Intel Corporation
Graphics Architect
Education:
University of Nebraska - Lincoln 1983 - 1990
Bachelors, Bachelor of Science
Skills:
Computer Architecture
Semiconductors
Soc
Intel
Microprocessors
Cross Functional Team Leadership
C
C++
Debugging
Product Management
Embedded Systems
Silicon
Asic
Verilog
Power Management

Publications

Us Patents

Method, Apparatus, And System For High Speed Data Transfer Using Source Synchronous Data Strobe

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US Patent:
6621760, Sep 16, 2003
Filed:
Mar 31, 2000
Appl. No.:
09/541140
Inventors:
Abid Ahmad - Folsom CA
Katen Shah - Orangevale CA
Alankar Saxena - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 800
US Classification:
365233, 365194, 365193
Abstract:
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Method, Apparatus, And System For High Speed Data Transfer Using Source Synchronous Data Strobe

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US Patent:
6839290, Jan 4, 2005
Filed:
Sep 15, 2003
Appl. No.:
10/663235
Inventors:
Abid Ahmad - Folsom CA, US
Katen Shah - Orangevale CA, US
Alankar Saxena - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 700
US Classification:
365193, 365194, 365233
Abstract:
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.

Method, Apparatus, And System For High Speed Data Transfer Using Programmable Dll Without Using Strobes For Reads And Writes

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US Patent:
6851069, Feb 1, 2005
Filed:
Mar 30, 2000
Appl. No.:
09/539082
Inventors:
Abid Ahmad - Folsom CA, US
Katen Shah - Orangevale CA, US
Alankar Saxena - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 112
US Classification:
713503, 713401, 713500
Abstract:
According to one aspect of the invention, a method is provided in which a first clock signal is generated. A second clock signal is derived from the first clock signal. The second clock signal is delayed relative to the first clock signal by a first delay period by a delay locked loop (DLL) circuit. The second clock signal is used to latch incoming data from a memory device.

Interfacing A Digital Display Card Through Pci Express Connector

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US Patent:
7345689, Mar 18, 2008
Filed:
Dec 19, 2003
Appl. No.:
10/742216
Inventors:
Scott R. Janus - Rocklin CA, US
Katen A. Shah - Folsom CA, US
Adam H. Wilen - Folsom CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 13/14
G06F 3/00
US Classification:
345520, 345519, 710 8
Abstract:
An embodiment of the present invention is a technique to interface a display card through an interface connector. A video output device on the display card generates digital video output signals from a graphics chipset on a motherboard. The card is plugged into an interface connector on the motherboard. The interface connector is compatible with a first interface standard. The video output device is compatible to a second interface standard. A card detector is coupled to the video output device and the interface connector to enable the video output device if the graphics chip set supports the video output device.

System Co-Processor

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US Patent:
7907138, Mar 15, 2011
Filed:
Dec 29, 2006
Appl. No.:
11/648305
Inventors:
Katen Shah - Folsom CA, US
Hong Jiang - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 17/00
US Classification:
345420, 345505, 345520, 345522, 703 2, 710300, 718104, 713 93
Abstract:
Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

System Co-Processor

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US Patent:
8203557, Jun 19, 2012
Filed:
Feb 9, 2011
Appl. No.:
13/023562
Inventors:
Katen Shah - Folsom CA, US
Hong Jiang - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06T 17/00
US Classification:
345420, 345501, 345502, 345503, 345504, 345505, 345519, 345520, 345531, 345543
Abstract:
Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Concurrent Pci Express With Sdvo

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US Patent:
20060106911, May 18, 2006
Filed:
Oct 29, 2004
Appl. No.:
10/976488
Inventors:
James Chapple - Chandler AZ, US
Sylvia Downing - El Dorado Hills CA, US
Scott Janus - Rocklin State CA, US
Katen Shah - Folsom CA, US
Patrick Smith - Cameron Park CA, US
International Classification:
G06F 15/16
US Classification:
709200000
Abstract:
A method, apparatus, and system are disclosed. In one embodiment the method comprises transmitting Peripheral Component Interconnect (PCI) Express protocol data on a first set of one or more lanes of a link and concurrently transmitting non-PCI Express protocol data on a second set of one or more lanes of the link.

System Co-Processor

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US Patent:
20110273460, Nov 10, 2011
Filed:
Jul 14, 2011
Appl. No.:
13/182689
Inventors:
Katen Shah - Folsom CA, US
Hong Jiang - San Jose CA, US
International Classification:
G06F 15/80
US Classification:
345505
Abstract:
Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.
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Katen A Shah from Folsom, CA, age ~60 Get Report