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Kalyana R Kantipudi

from San Jose, CA
Age ~41
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Also known as:
Kalyana Kalyana
Phone and address:
2558 Alderwood Dr, San Jose, CA 95132
Connected to:
John Kantirakis, 45Perry M Kantner, 82Renee Kantner, 43Tina M Kantner, 40Kara L Kantola, 56Melissa L Kantola, 45Pam R Kantola, 72Patricia M Kantola, 73Peter T Kantola, 43Sarah E Kantola, 32

Kalyana Kantipudi Phones & Addresses

  • 2558 Alderwood Dr, San Jose, CA 95132
  • Sunnyvale, CA
  • Auburn, AL
  • Mobile, AL

Work

Company: Altera Mar 2010 Position: Senior test development engineer

Education

Degree: MS School / High School: Auburn University 2005 to 2006 Specialities: Electrical and Computer Engineering

Skills

Verilog • Asic • Debugging • Fpga • Test Development • Serdes • Ic • Tcl • Semiconductors • Soc • Dft • Perl • Rtl Design • Field Programmable Gate Arrays

Industries

Semiconductors

Resumes

Resumes

Kalyana Kantipudi Photo 1

Chief Engineer

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Location:
250 west Glenn Ave, Auburn, AL 36830
Industry:
Semiconductors
Work:
Altera since Mar 2010
Senior Test Development Engineer
Altera Dec 2006 - Mar 2010
Advanced Test Development Engineer
Education:
Auburn University 2005 - 2006
MS, Electrical and Computer Engineering Acharya Nagarjuna Vishwavidhyalayamu
Skills:
Verilog
Asic
Debugging
Fpga
Test Development
Serdes
Ic
Tcl
Semiconductors
Soc
Dft
Perl
Rtl Design
Field Programmable Gate Arrays

Publications

Us Patents

Clock Control Circuitry And Methods Of Utilizing The Clock Control Circuitry

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US Patent:
8621303, Dec 31, 2013
Filed:
Jan 20, 2012
Appl. No.:
13/354706
Inventors:
Kalyana Ravindra Kantipudi - Sunnyvale CA, US
Dhwani Shah - San Jose CA, US
Jayabrata Ghosh Dastidar - Campbell CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/28
US Classification:
714731, 714726
Abstract:
A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element.

Automatic Test Pattern Generation System For Programmable Logic Devices

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US Patent:
8516322, Aug 20, 2013
Filed:
Sep 28, 2009
Appl. No.:
12/568136
Inventors:
Jayabrata Ghosh Dastidar - Santa Clara CA, US
Alok Shreekant Doshi - Sunnyvale CA, US
Binh Vo - Los Gatos CA, US
Kalyana Ravindra Kantipudi - Sunnyvale CA, US
Sergey Timokhin - Palo Alto CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G01R 31/3183
G01R 31/40
US Classification:
714738, 714725
Abstract:
A programmable integrated circuit may contain multiple logic blocks. Computing equipment may be used to run automated tools that process a design for the programmable integrated circuit to perform corresponding circuit tests. A translation tool may translate a transistor-level description of circuitry on the programmable integrated circuit into a gate-level description. A block-level test configuration data generation tool may generate block-level test configuration data files. The test configuration data files may be used as constraints for an automatic test pattern generation tool that produces block-level test vectors. A full-chip propagation tool may use the block-level test vectors, block-level test configuration data files, and full-chip constraints to produce corresponding full-chip test configuration data and full-chip test vectors for testing the integrated circuit. A translation tool may convert the configuration data and test vectors into a tester file.

Integrated Circuits With In-Field Diagnostic And Repair Capabilites

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US Patent:
20190101906, Apr 4, 2019
Filed:
Sep 29, 2017
Appl. No.:
15/720539
Inventors:
- Santa Clara CA, US
Gregory Steinke - Saratoga CA, US
Adam J. Wright - Santa Clara CA, US
Kalyana Ravindra Kantipudi - Sunnyvale CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G05B 19/418
Abstract:
An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.

Methods And Apparatus For Detecting Defects In Memory Circuitry

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US Patent:
20180301201, Oct 18, 2018
Filed:
Apr 12, 2017
Appl. No.:
15/485543
Inventors:
- Santa Clara CA, US
Kalyana Ravindra Kantipudi - Sunnyvale CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G11C 29/10
G11C 29/52
Abstract:
A method of screening for configuration-related defects in integrated circuits is provided. To detect configuration defects, test pattern configuration data and error correction data for that test pattern are loaded into configuration memory. Existing cyclic redundancy check circuitry on the integrated circuit is recruited to compute check-sum signatures based on the data stored in each frame of the memory array. Defects in configuration memory cells and configuration-related circuitry are identified by comparing the error correction data of frame to the computed check-sum signature of a frame. Localized freezing of programmable logic associated with configuration memory is optionally applied to eliminate data contention and ensure maximum coverage of the memory array during screening. Several test patterns of configuration data are also provided.
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Kalyana R Kantipudi from San Jose, CA, age ~41 Get Report