Resumes
Resumes
Jose Valdepenas
View pageIndustry:
Information Technology and Services
Jose Valdepenas Phones & Addresses
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Boynton Beach, FL
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16091 Rosecroft Ter, Delray Beach, FL 33446 (561) 404-4111
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Allston, MA
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1010 46Th St, Pompano Beach, FL 33069 (954) 917-3013
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3 Unicorn Way, Nashua, NH 03063 (603) 886-0045 (603) 886-3541 (603) 880-0914
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Chelsea, MA
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Malden, MA
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Fort Lauderdale, FL
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Palm Beach, FL
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3 Unicorn Way, Nashua, NH 03063 (603) 886-3541
Work
Position:
Executive, Administrative, and Managerial Occupations
Education
Degree:
Associate degree or higher
Industries
Information Technology and Services
Publications
Us Patents
High-Speed, High-Capacity, Fault-Tolerant Error-Correcting Storage System
View pageUS Patent:
49425790, Jul 17, 1990
Filed:
Feb 27, 1989
Appl. No.:
7/317048
Inventors:
Theodore J. Goodlander - Nashua NH
Jose M. Valdepenas - Nashua NH
Ricardo E. V. McCaskey - Nashua NH
Gerardo Vizcaino - Nashua NH
Jose M. Valdepenas - Nashua NH
Ricardo E. V. McCaskey - Nashua NH
Gerardo Vizcaino - Nashua NH
Assignee:
Cab-Tek, Inc. - Nashua NH
International Classification:
G06F 1110
G06F 1116
G06F 1116
US Classification:
371 51
Abstract:
A storage system for dynamic and trasparent error correction has a number of first individual storage devices for information and a second individual storage device for error code bits that are used to correct the information when one of the storage devices detects an error. Each error code bit is generated from the information at respective bit positions across the first storage devices. Storage device controllers are connected between a user CPU interface and respective storage devices for operating them concurrently. The interface includes an interface CPU for controlling the storage device controllers and translating the interface convention of user CPU requests into the interface convention of the storage devices. A buffer memory is connected to data surface associated with the respective storage devices. The interface CPU includes logic for immediately acknowledging a write to the associated storage device upon the data being placed in the buffer memory.