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Jonathan P Ebbers

from South Burlington, VT
Age ~42
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Also known as:
Jonathan Phillip Ebbers, Jonathan Philli Ebbers, Jonathan H Ebbers
Phone and address:
24 Gilbert St, Burlington, VT 05403
Connected to:
Anne M Ebbers, 38Corey R Ebbers, 46Cynthia K Ebbers, 74David L Ebbers, 81Deziree D Ebbers, 46Geo Ebbers, 113Gwen B Ebbers, 58Joanna R Ebbers, 55Joshua P Ebbers, 43Laura B Ebbers, 64

Jonathan Ebbers Phones & Addresses

  • 24 Gilbert St, South Burlington, VT 05403
  • 8 Butler Dr, S Burlington, VT 05403
  • 3 River St, Essex Junction, VT 05452
  • S Burlington, VT
  • 33 Hillside Cir, Essex Junction, VT 05452

Work

Company: Virence health Jul 2018 to Feb 2019 Position: Technical lead

Education

Degree: Bachelors, Bachelor of Science School / High School: Penn State University 2000 to 2004 Specialities: Computer Engineering

Skills

Debugging • Perl • Testing • Healthcare Information Technology • Hl7 • Computer Architecture • Verilog • Software Design • Software Engineering • Semiconductors • Linux • Functional Verification • Hardware Architecture • Systemverilog • C++ • Fpga • Intersystems Cache • Sdlc • Sql • Vera • Revenue Cycle Management • Interfaces • Embedded Systems • Vhdl • Hospital Revenue Cycle • Software Implementation • Processors • Arm • Agile Methodologies • Firmware • Process Improvement • Shell Scripting • Innovation

Industries

Information Technology And Services

Resumes

Resumes

Jonathan Ebbers Photo 1

Technical Lead

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Location:
8 Butler Dr, South Burlington, VT 05403
Industry:
Information Technology And Services
Work:
Virence Health Jul 2018 - Feb 2019
Technical Lead
Athenahealth Jul 2018 - Feb 2019
Technical Lead
Ge Healthcare Nov 2013 - Jul 2018
Technical Engagement Lead
Ge Healthcare Jun 2010 - Nov 2013
Software Engineer
Ibm Jan 2005 - Jun 2010
Verification Engineer
Education:
Penn State University 2000 - 2004
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Debugging
Perl
Testing
Healthcare Information Technology
Hl7
Computer Architecture
Verilog
Software Design
Software Engineering
Semiconductors
Linux
Functional Verification
Hardware Architecture
Systemverilog
C++
Fpga
Intersystems Cache
Sdlc
Sql
Vera
Revenue Cycle Management
Interfaces
Embedded Systems
Vhdl
Hospital Revenue Cycle
Software Implementation
Processors
Arm
Agile Methodologies
Firmware
Process Improvement
Shell Scripting
Innovation

Publications

Us Patents

System-On-Chip (Soc), Design Structure And Method

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US Patent:
7904872, Mar 8, 2011
Filed:
May 22, 2008
Appl. No.:
12/125255
Inventors:
Jonathan P. Ebbers - Essex Junction VT, US
Todd E. Leonard - Williston VT, US
Kyle E. Schneider - Bristol VT, US
Peter A. Twombly - Shelburne VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716138, 716100
Abstract:
Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

System-On-Chip (Soc), Design Structure And Method

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US Patent:
7904873, Mar 8, 2011
Filed:
May 22, 2008
Appl. No.:
12/125269
Inventors:
Jonathan P. Ebbers - Essex Junction VT, US
Todd E. Leonard - Williston VT, US
Kyle E. Schneider - Bristol VT, US
Peter A. Twombly - Shelburne VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716138, 716100
Abstract:
Disclosed is a system-on-chip (SOC) structure that allows for automated integration of multiple intellectual cores. The SOC structure incorporates a plurality of cells connected to a common bus on a chip. Each cell incorporates a functional core and an automated integration unit (AIU) connected to the functional core. Each AIU communicates integration information for its functional core over the common bus to the AIUs in the other cells. The exchange of information between the AIUs is controlled either by the integration units themselves or by a controller. Based on received integration information, each AIU can automatically make any required configuration adjustments for integration. Furthermore, based on this exchange of information, the functional cores can interact, as necessary, during SOC operation. Also disclosed are an associated method of forming such a SOC structure and a design structure for such an SOC structure.

Dynamically Reconfigurable Self-Monitoring Circuit

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US Patent:
8407633, Mar 26, 2013
Filed:
Oct 26, 2009
Appl. No.:
12/605417
Inventors:
Adam J. Courchesne - Essex Junction VT, US
Jonathan P. Ebbers - Essex Junction VT, US
Kenneth J. Goodnow - Essex Junction VT, US
Suzanne Granato - Essex Junction VT, US
Eze Kamanu - Essex Junction VT, US
Kyle E. Schneider - Essex Junction VT, US
Peter A. Twombly - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716101, 716104
Abstract:
A method configures a plurality of circuit elements for execution of an application in a first configuration. The method monitors the execution of the application on the plurality of circuit elements to produce monitoring information, using a computerized device, and stores the monitoring information in a storage structure. The method selectively communicates the monitoring information to an external element separate from the computerized device. The external element transforms the first configuration into a second configuration based on the monitoring information. The computerized device receives the second configuration from the external element and reconfigures the plurality of elements into the second configuration.

Switch To Perform Non-Destructive And Secure Disablement Of Ic Functionality Utilizing Mems And Method Thereof

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US Patent:
8436638, May 7, 2013
Filed:
Dec 10, 2010
Appl. No.:
12/964764
Inventors:
Jonathan Ebbers - South Burlington VT, US
Kenneth J. Goodnow - Essex Junction VT, US
Stephen G. Shuma - Underhill VT, US
Peter A. Twombly - Shelburne VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19/00
US Classification:
326 8, 326 9, 326 38
Abstract:
Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled when the MEMS device is in the error state.

Microelectromechanical Structure (Mems) Monitoring

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US Patent:
8513948, Aug 20, 2013
Filed:
Nov 22, 2010
Appl. No.:
12/951515
Inventors:
Jonathan P. Ebbers - South Burlington VT, US
Kenneth J. Goodnow - Essex VT, US
Stephen Gerard Shuma - Underhill VT, US
Peter A. Twombly - Shelburne VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/327
G01R 27/26
US Classification:
324415, 324658
Abstract:
A MEMS component is monitored to determine its status. Sensors are deployed to sense the MEMS component and produce detection signals that are analyzed to determine the MEMS component state. An indicator device alerts a user of the status, particularly if the MEMS component has failed. Additionally, the MEMS component monitoring system may be practiced as a design structure encoded on computer readable storage media as part of a circuit design system.

Generating Test Coverage Bin Based On Simulation Result

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US Patent:
20090210746, Aug 20, 2009
Filed:
Feb 19, 2008
Appl. No.:
12/033239
Inventors:
Bruce J. Ditmyer - Westford VT, US
Susan Farmer Bueti - Waterbury VT, US
Jonathan P. Ebbers - Essex Junction VT, US
Suzanne Granato - Essex Junction VT, US
Francis A. Kampf - Jeffersonville VT, US
Barbara L. Powers - Hinesburg VT, US
Louis Stermole - Jericho VT, US
International Classification:
G06F 11/00
US Classification:
714 26, 714 45, 714E11001
Abstract:
A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Design Structure For Automated Means For Determining Internet Access On A System On A Chip

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US Patent:
20100011138, Jan 14, 2010
Filed:
Jul 9, 2008
Appl. No.:
12/170166
Inventors:
Jonathan Phillip Ebbers - Essex Junction VT, US
Kenneth Joseph Goodnow - Essex VT, US
Todd Edwin Leonard - Williston VT, US
Peter Albert Twombly - Shelburne VT, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 13/14
US Classification:
710107
Abstract:
A method for determining Internet access by an autonomous electronic circuit on a system on a chip integrated circuit includes a system bus which is snooped to determine if Internet activity is occurring on the system bus. Local header information is collected when the snooping has determined that Internet activity is occurring on the system bus. A packet including the local header information is created. Internet access is requested with the created packet.
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Jonathan P Ebbers from South Burlington, VT, age ~42 Get Report