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John J Pekarik

from Underhill, VT
Age ~61
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Also known as:
Jack J Pekarik
Phone and address:
328 Poker Hill Rd, Underhill Flats, VT 05489
(802) 858-9194
Related to:
Molly T Pekarik, 33Audrey Pekarik, 30
Connected to:
Christopher Pekarik, 58Matthew D Pekarna, 66Heidi Pekarsky, 65Jerome E Pekarski, 58Mark M Pekarske, 59Oleksandra Pekarska, 41Vincent J Pekarski, 91Wade J Pekarske, 52Yuri A Pekarsky, 57Rosemary M Pekary, 74

John Pekarik Phones & Addresses

  • 328 Poker Hill Rd, Underhill, VT 05489 (802) 858-9194
  • Colchester, VT
  • Pottsville, PA
  • Goleta, CA
  • Underhill Ctr, VT
  • Hinesburg, VT

Public records

Vehicle Records

John Pekarik

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Address:
328 Poker Hl Rd, Underhill, VT 05489
Phone:
(802) 899-5030
VIN:
JHLRE4H77AC007225
Make:
HONDA
Model:
CR-V
Year:
2010

Publications

Us Patents

Borderless Contact To Diffusion With Respect To Gate Conductor And Methods For Fabricating

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US Patent:
6498096, Dec 24, 2002
Filed:
Mar 8, 2001
Appl. No.:
09/800911
Inventors:
James Allan Bruce - Williston VT
Jonathan Daniel Chapple-Sokol - Essex Junction VT
Michael James Lercel - Williston VT
Randy William Mann - Jericho VT
James Spiros Nakos - Essex VT
John Joseph Pekarik - Underhill VT
Kirk David Peterson - Essex Junction VT
Jed Hickory Rankin - Burlington VT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2144
US Classification:
438666, 438585
Abstract:
A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Electric Pumping Of Rare-Earth-Doped Silicon For Optical Emission

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US Patent:
6795468, Sep 21, 2004
Filed:
Jun 16, 2003
Appl. No.:
10/461919
Inventors:
John J. Pekarik - Underhill VT
Walter J. Varhue - Georgia VT
Assignee:
Internatioal Business Machines Corporation - Armonk NY
International Classification:
H01S 500
US Classification:
372 44, 372 43
Abstract:
A structure having a p-n junction in a semiconductor having a first p-type region and a first n-type region along with a region located in the vicinity of the p-n junction that is doped with a rare-earth element. In addition, the structure includes a charge source coupled to one of the p-type region and n-type region for providing charge carriers to excite atoms of the rare-earth element. Also provided is a method for producing the structure that includes providing a bipolar junction transistor; doping a region in a collector of the transistor with a rare-earth element; and biasing the transistor to generate light emission from the rare-earth element doped region.

Integrated Circuit Having Pairs Of Parallel Complementary Finfets

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US Patent:
6943405, Sep 13, 2005
Filed:
Jul 1, 2003
Appl. No.:
10/604206
Inventors:
Andres Bryant - Essex Junction VT, US
David M. Fried - Ithaca NY, US
Mark D. Jaffe - Shelburne VT, US
Edward J. Nowak - Essex Junction VT, US
John J. Pekarik - Underhill VT, US
Christopher S. Putnam - Hinesburg VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/00
H01L029/76
US Classification:
257327, 257329, 257330, 257347, 257350, 257369, 438154, 438157, 438164
Abstract:
A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET.

Field Effect Transistor Having An Asymmetrically Stressed Channel Region

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US Patent:
7355221, Apr 8, 2008
Filed:
May 12, 2005
Appl. No.:
10/908448
Inventors:
Gregory G. Freeman - Hopewell Junction NY, US
Anil K. Chinthakindi - Wappingers Falls NY, US
David R. Greenberg - White Plains NY, US
Basanth Jagannathan - Schaumburg IL, US
Marwan H. Khater - Poughkeepsie NY, US
John Pekarik - Underhill VT, US
Xudong Wang - Essex Junction VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
US Classification:
257213, 257192, 257E51006, 257E2706
Abstract:
A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

Method And Apparatus For Improving Integrated Circuit Device Performance Using Hybrid Crystal Orientations

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US Patent:
7382029, Jun 3, 2008
Filed:
Jul 29, 2005
Appl. No.:
11/161337
Inventors:
John J. Pekarik - Underhill VT, US
Xudong Wang - Groton MA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
H01L 21/8234
US Classification:
257392, 257391, 257627, 438275, 438152
Abstract:
A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of the first conductivity type on a second portion of the substrate having a second crystal lattice orientation. The carrier mobility of the first device formed on the first crystal lattice orientation is greater than the carrier mobility of the second device formed on the second crystal lattice orientation.

Multi-Level Interconnections For An Integrated Circuit Chip

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US Patent:
7414275, Aug 19, 2008
Filed:
Jun 24, 2005
Appl. No.:
11/160463
Inventors:
David Ross Greenberg - White Plains NY, US
John Joseph Pekarik - Underhill VT, US
Jorg Scholvin - Cambridge MA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/41
US Classification:
257211, 257203, 257207, 257208, 257750, 257752, 257758, 257767, 257774, 257E23142, 257E23143, 257E23144, 257E23145, 257E23151, 257E23152, 257E23153
Abstract:
Multilevel metallization layouts for an integrated circuit chip including transistors having first, second and third elements to which metallization layouts connect. The layouts minimize current limiting mechanism including electromigration by positioning the connection for the second contact vertically from the chip, overlapping the planes and fingers of the metallization layouts to the first and second elements and forming a pyramid or staircase of multilevel metallization layers to smooth diagonal current flow.

Semiconductor Devices Having Torsional Stresses

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US Patent:
7462916, Dec 9, 2008
Filed:
Jul 19, 2006
Appl. No.:
11/458461
Inventors:
Richard Q. Williams - Essex Junction VT, US
Dureseti Chidambarrao - Weston CT, US
John J. Ellis-Monaghan - Grand Isle VT, US
Shreesh Narasimha - Beacon NY, US
Edward J. Nowak - Essex Junction VT, US
John J. Pekarik - Underhill VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
US Classification:
257395, 257396, 257397, 257506, 257524, 257E2902
Abstract:
A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.

Integrated Circuit Having Pairs Of Parallel Complementary Finfets

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US Patent:
7517806, Apr 14, 2009
Filed:
Jul 21, 2005
Appl. No.:
11/186748
Inventors:
Andres Bryant - Essex Junction VT, US
David M. Fried - Ithaca NY, US
Mark D. Jaffe - Shelburne VT, US
Edward J. Nowak - Essex Junction VT, US
John J. Pekarik - Underhill VT, US
Christopher S. Putnam - Hinesburg VT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/302
US Classification:
438734, 438164, 438197, 438736, 438737, 438595, 438696, 438300, 438947, 438585, 438587, 438399
Abstract:
A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET.
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John J Pekarik from Underhill, VT, age ~61 Get Report